Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-03-22
2011-03-22
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S103000, C716S132000, C716S136000, C703S016000
Reexamination Certificate
active
07913204
ABSTRACT:
A high-level synthesis apparatus for automatically generating a register transfer level (RTL) logic circuit from a behavioral description has a scheduling unit configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description, a scheduling result inputting/outputting unit configured to extract a point to be allocated to a register from the data flow graph and output register information indicating the point, the scheduling result inputting/outputting unit being provided with dynamic analysis data that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation, an allocating unit configured to consult dynamic analysis data and allocate circuit elements to the behavioral description, and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit.
REFERENCES:
patent: 5854929 (1998-12-01), Van Praet et al.
patent: 6832363 (2004-12-01), Ohnishi
patent: 6968523 (2005-11-01), Masuda
patent: 7120903 (2006-10-01), Toi et al.
patent: 7266791 (2007-09-01), Morishita et al.
patent: 2002/0188923 (2002-12-01), Ohnishi
patent: 2003/0061601 (2003-03-01), Toi et al.
patent: 2004/0111684 (2004-06-01), Masuda
patent: 2004/0123249 (2004-06-01), Sato et al.
patent: 2005/0010387 (2005-01-01), Morishita et al.
patent: 2006/0130029 (2006-06-01), Morishita et al.
Miyaoka et al., “A CoSynthesis Algorithm for Application Specific Processors With Heterogeneous Datapaths”, Proceedings of the ASP-DAC 2004 Design Automation Conference, Jan. 27-30, 2004, pp. 250-255.
Srinivasan et al., “Fine-Grained and Coarse-Grained Behavioral Partitioning with Effective Utilization of Memory and Design Space Exploration for Multi-FPGA Architectures”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, No. 1, Feb. 2001, pp. 140-158.
Theobald et al., “Transformations for the Synthesis and Optimization of Asynchronous Distributed Control”, Proceedings of 2001 Design Automation Conference, 2001, pp. 263-268.
Kabushiki Kaisha Toshiba
Kik Phallaka
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
LandOfFree
High-level synthesis apparatus, high-level synthesis system... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-level synthesis apparatus, high-level synthesis system..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-level synthesis apparatus, high-level synthesis system... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2732019