High level self-checking intelligent I/O controller

Details High level self-checking intelligent I/O controller High level self-checking intelligent I/O controller

1987-06-30

1988-11-15

Atkinson, Charles E.

Excavating

G06F 1116

Patent

active

047854537

ABSTRACT:
The present invention is an input/output controller for providing total data integrity for any single point failure. The I/O controller comprises a processor module having two microprocessors, an associated memory, a direct memory access module ("DMA"), and a processor support module ("PSM"); a device drive interface; and a channel interface. The two microprocessors are operated in lockstep as a dual modular redundant processor system. The processors provide true and complement, respectively, addresses, data and control strobes. The PSM compares the true and complement data to detect errors (i.e., corresponding data bits not being a true-complement pair) and generates parity protected data (and checks parity) on the data bus. The PSM also generates and checks dual railed control strobes and provides synchronization of all control strobes and interrupt signals to enable the tru-complement pair of microprocessors to operate in lockstep. The DMA compares the redundant addresses from the processors to detect errors and to generate parity protected addresses (and check parity) on the address bus. The DMA also generates the checks bus arbitration signals and controls direct memory access. Self-checking checkers are used to check the various dual railed, true-complement pairs of signals to detect, locate and isolate internal faults. Mis-compares between true-complement address, data and control signals and parity errors detected in reading program instructions from memory all are treated as fatal errors, which cause both processors to halt. Other types of errors are treated as nonfatal, which cause processor exceptions during which appropriate programming is executed to locate and isolate such errors.

REFERENCES:
patent: 3517174 (1970-06-01), Ossfeldt
patent: 3559167 (1971-01-01), Carter et al.
patent: 3602886 (1971-08-01), Carter et al.
patent: 3859513 (1975-01-01), Chuang et al.
patent: 4012717 (1977-03-01), Censier et al.
patent: 4020460 (1977-04-01), Jones et al.
patent: 4070648 (1978-01-01), Merganthaler et al.
patent: 4096990 (1978-06-01), Strelow
patent: 4342112 (1982-07-01), Stodola
patent: 4358823 (1982-11-01), McDonald et al.
patent: 4400792 (1983-08-01), Strelow
patent: 4412280 (1983-10-01), Murphy et al.
patent: 4541094 (1985-09-01), Stiffler
patent: 4590549 (1986-05-01), Burrage et al.

Affiliated with

Also associated with

Rating

High level self-checking intelligent I/O controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High level self-checking intelligent I/O controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High level self-checking intelligent I/O controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1107751