High-level data link control packet assembler/disassembler

Multiplex communications – Wide area network – Packet switching

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Details

370 941, H04L 1100

Patent

active

049512781

ABSTRACT:
A data communications system has a layered communication architecture including network services protocols including a link layer and higher level protocols, and has IBM or IBM-compatible synchronous data link control (SDLC) devices including a host computer and a plurality of end user devices desiring to communicate across an X.25 packet-switching network (PSN) of the communications system. A packet assembler/disassembler (PAD) support X.25 communication across the PSN between the SDLC-utilizing host computer and the SDLC-utilizing end user device. In one embodiment, separate high level data link control (HDLC) PADs are provided at each end of the PSN operationally associated with the host computer and the plurality of end user devices, respectively. The PADS generate and respond to at least three formats of SDLC commands and responses, and, in association with their respective SDLC devices, perform at least four functions including a call setup phase, a data transfer phase, a call clearing phase, and handling of abnormal conditions. PAD means comprises qualified logical link control (QLLC) PAD means located at an end of said packet switching network for either operational association with said host computer or operational association with said plurality of end user devices. In another embodiment, a single qualified logical link control (QLLC) PAD performs functions similar to those of the HDLC PAD embodiment, except that rather than having a PAD at both ends (host end and terminal end) of a connection, a PAD is provided at only one end of the connection.

REFERENCES:
patent: 4058672 (1977-11-01), Crager et al.
Lars-Erik Logdberg, Eripax, a Data Communication System, Ericsson Review No. 2, 1983.

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