High level circuit design synthesis using transformations

Details High level circuit design synthesis using transformations High level circuit design synthesis using transformations

1994-06-03

1996-08-27

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

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active

055507492

ABSTRACT:
A method of high level circuit design synthesis using transformations based upon the addition of deflection operations reduces the interconnects and register requirements as well as the area requirements of a circuit design while preserving throughput without increasing the number of execution units needed. The method may also be applied to reduce the partial scan overhead for generating testable datapaths. The overall result of the transformations is to improve resource utilization and/or testability of circuits so designed.

REFERENCES:
patent: 5359537 (1994-10-01), Saucier et al.
patent: 5359538 (1994-10-01), Hui et al.
"PASCANT: A Partial Scan and Test Generation System" by Sudipta Bhawmik et al, IEEE Custom Integrated Circuit Conf., May 12-15, 1991, pp. 17.3.1-17.3.4.
Sujit Dey et al, "Exploiting Hardware Sharing in High-Level Synthesis for Partial Scan Optimization", paper B.1, ICCAD93, Nov. 1993, pp. 20-25.

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