High latency timing circuit

Details High latency timing circuit High latency timing circuit

2007-12-04

2007-12-04

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S00100A, C331S017000, C331S016000, C327S156000, C360S046000, C360S051000, C375S376000, C713S400000

Reexamination Certificate

active

11507916

ABSTRACT:
A phase locked loop (PLL) circuit, comprises a frequency integrator circuit that receives a target signal, a phase shift signal and a frequency gain correction parameter and that selectively disables tracking frequency offset based on a value of the frequency gain correction parameter. A phase integrator circuit communicates with frequency integrator circuit, that synchronizes phase with the target signal and generates a phase signal. A phase shift measurement circuit generates the phase shift signal based on the phase signal. A phase interpolator circuit generates the frequency gain correction parameter based on the phase signal.

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