High integrity digital processor architecture

Details High integrity digital processor architecture High integrity digital processor architecture

1986-03-31

1988-06-14

Lall, Parshotam S.

Boots, shoes, and leggings

364424, 364200, 371 12, G06F 1550, G06F 1100, G06F 1200

Patent

active

047516704

ABSTRACT:
A digital data processor architecture immune from digital computer upset including a non-volatile random access memory for storing past and present values of state variables. An index counter is utilized to offset the store and retrieve instruction base addresses to effect the multiple storage of the state variables in the non-volatile memory. A monitor detects disruptions in data processing and vectors the processor to a reinitialization and restart routine in which the past values of the state variables are utilized.

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Barner et al, "Automatic Restart and Checkpoint Retry for an Unattended Earth Station in a Satellite Communication Network", 10/79, pp. 1987-1989, IBM Technical Disclosure Bulletin, vol. 22, No. 5.
Hicks et al, "Instruction Retry Mechanism for a Computer", 1/75, pp. 2239-2242, IBM Technical Disclosure Bulletin, vol. 17, No. 8.

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