High integrity borderless vias with protective sidewall spacer

Details High integrity borderless vias with protective sidewall spacer High integrity borderless vias with protective sidewall spacer

1998-06-15

1999-11-09

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257758, 257774, H01L 2348

Patent

active

059820357

ABSTRACT:
High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.

REFERENCES:
patent: 5619072 (1997-04-01), Mehta
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5757077 (1998-05-01), Chung et al.

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