High-integration J-K flip-flop circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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Details

327203, H03K 3356

Patent

active

055326340

ABSTRACT:
This invention relates to a J-K flip-flop circuit which achieves a decrease in area required on an integrated circuit and a reduction of cost. Three N-MOSFETs, whose gates respectively receive a clock CL1, a J signal, and a signal from one node of a second flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to one node of a first flip-flop circuit. Three N-MOSFETs, whose gates respectively receive the clock CL1, a K signal, and a signal from the other node of the second flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to the other node of the first flip-flop circuit. Two N-MOSFETs, whose gates respectively receive a clock CL2 and a signal from one node of the first flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to the other node of the second flip-flop circuit. Two N-MOSFETs, whose gates respectively receive the clock signal CL2 and a signal from the other node of the first flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to one node of the second flip-flop circuit. The other end of each of these series connections is connected to a ground voltage.

REFERENCES:
patent: 4350905 (1982-09-01), Sato
patent: 4356411 (1982-10-01), Suzuki et al.
patent: 4512029 (1985-04-01), Brice
patent: 4806786 (1989-02-01), Valentine
patent: 5140179 (1992-08-01), Takano
patent: 5170074 (1992-12-01), Aoki

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