High integration DRAM controller

Details High integration DRAM controller High integration DRAM controller

1992-09-23

1994-04-26

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

36523003, 3652385, 395425, G11C 800

Patent

active

053073207

ABSTRACT:
A memory controller for a dynamic random access memory (DRAM) is described. The memory controller of the present invention provides access to a memory array which uses DRAM banks. The memory controller is adaptable to various types of DRAM banks, such that the memory array is capable of having independent and different configurations of DRAM banks in the memory. The memory controller includes multiple programmable storage registers, where one register is associated with every bank location in the memory array. Each of the programmable registers is independently programmed to contain access parameters that are necessary to access its associated bank. The memory controller of the present invention also includes circuitry which is configured to provide each of the banks in the memory with its necessary control signals in the proper sequence and timing according to the access parameters in its associated storage register. In this manner, the present invention is capable of accommodating DRAM banks of different types in the memory array.

REFERENCES:
patent: 4725945 (1988-02-01), Kronstadt et al.
patent: 4937791 (1990-06-01), Steele et al.
patent: 4967397 (1990-10-01), Walck
patent: 5175835 (1992-12-01), Beighe et al.

Affiliated with

Also associated with

Rating

High integration DRAM controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High integration DRAM controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High integration DRAM controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1717196