High instruction fetch bandwidth in multithread processor...

Details High instruction fetch bandwidth in multithread processor... High instruction fetch bandwidth in multithread processor...

2005-05-24

2005-05-24

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

C711S140000, C711S213000, C712S206000, C712S245000

Reexamination Certificate

active

06898694

ABSTRACT:
The present invention provides a mechanism for supporting high bandwidth instruction fetching in a multi-threaded processor. A multi-threaded processor includes an instruction cache (I-cache) and a temporary instruction cache (TIC). In response to an instruction pointer (IP) of a first thread hitting in the I-cache, a first block of instructions for the thread is provided to an instruction buffer and a second block of instructions for the thread are provided to the TIC. On a subsequent clock interval, the second block of instructions is provided to the instruction buffer, and first and second blocks of instructions from a second thread are loaded into a second instruction buffer and the TIC, respectively.

REFERENCES:
patent: 5170476 (1992-12-01), Laakso et al.
patent: 5317701 (1994-05-01), Reininger et al.
patent: 5442756 (1995-08-01), Grochowski et al.
patent: 5724565 (1998-03-01), Dubey et al.
patent: 6170051 (2001-01-01), Dowling
patent: 6237074 (2001-05-01), Phillips et al.

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