Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-12-20
2002-08-13
Patel, Rajnikant B. (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C323S314000, C327S066000
Reexamination Certificate
active
06433528
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to regulated current sources and more particularly to a high-impedance current source having an enhanced compliance voltage.
BACKGROUND OF THE INVENTION
In today's analog low-voltage circuits it is desirable to provide enhanced current source functionalities such as the biasing of differential pairs with high impedance current sources. Current mirrors can be used to provide such enhanced functionalities. Current mirrors replicate at their outputs the currents present at their inputs and are widely used in the electronics industry. There are many variations of the basic current mirror that may provide such functionalities. Regular cascode, high-swing cascode, regulated cascode, low voltage current, and active-input regulated cascode mirrors are some of the known current source solutions utilized in the electronics industry to provide biasing of differential pairs. Mirroring functionality is quite useful in many circuit applications such as a regulated current source for transconductance amplifiers and high-speed digital receivers. A basic current mirror is illustrated in FIG.
1
.
The basic current mirror
10
comprises two p-channel MOS transistors M
11
and M
12
having their gates
11
and
12
connected together and their sources
13
and
14
connected to a supply voltage V
DD
. To optimize the operation of the current mirror
10
, transistors M
11
and M
12
are biased to operate in the saturated region on or near the boundary between the linear and saturated regions, that is, the output characteristic is: V
DS
=V
GS
−V
T
where
V
DS
=drain to source voltage
V
GS
=gate to source voltage
V
T
=threshold voltage
In this configuration, a source-drain current of a MOS transistor has a positive dependence upon not only the gate voltage but also the source-drain voltage in the saturated region. If the source-drain voltage increases and the gate voltage is maintained at a constant level, the source-drain current correspondingly increases. This phenomenon is called “Early effect”. Early effect can be reduced by increasing the length of the PMOS transistors M
11
and M
12
. The dependence of source drain voltage is responsible for the very low output resistance of this configuration. The current mirror circuit of
FIG. 1
has been employed in current sources in the prior art.
FIG. 2
shows a regular cascode current mirror
20
. With the regular cascode mirror
20
, a current I
in
from the current source
27
flows through transistor M
3
, and a corresponding gate-source voltage appears between gate
27
and source
35
of the transistor M
3
. This gate-source voltage is determined in accordance with the characteristics of transistor M
3
and by the current I
in
supplied from the constant current source
27
. The current through transistor M
2
mirrors the current through transistor M
1
. Likewise the current through transistor M
4
mirrors the current through transistor M
3
. By adjusting the relative dimensions of transistors M
1
and M
2
and of transistors M
3
and M
4
, a desired output current can be achieved.
This regular cascode current mirror
20
is a well-known scheme that enhances the output impedance of the circuit. However, it suffers from a lack of headroom, i.e., it begins to operate several 100 mv above the threshold voltage of a PMOS transistor, thus lowering the operating headroom left to other circuitry operations.
FIG. 3
illustrates a high-swing cascode current mirror
40
. For the same output impedance as the regular cascode current mirror
20
, the dynamics are improved. By a careful design of the cascode bias circuit, the need of at least one threshold voltage at the output is avoided. Nevertheless, both of the transistors in the output branch have to be in saturation mode.
Referring now to
FIG. 4
there is shown a prior art regulated current mirror
50
. This scheme uses feedback circuitry that controls the drain source voltage of the MOS transistor M
2
. Its output resistance is therefore multiplied by the feedback gain factor and will be one order of magnitude higher than a usual cascode scheme.
A low-voltage current mirror
60
is illustrated in FIG.
5
. In this scheme if it is assumed that MOS transistors M
1
and M
2
have similar transconductance and output resistance, it can be shown that the output resistance is equal to the resistance of the current source driving transistor M
1
(R
1
In
). Using this technique, the output resistance can be high and the compliance voltage is very low. However, an active part or operational transconductance amplifier (OTA) is required.
FIG. 6
illustrates an active-input regulated cascode current mirror
70
. This mirror scheme requires two OTAs. Compliance voltage and output resistance are increased due to feedback. However, if performance, consumption and cost are considered, it does not appear as a good solution.
The above describe prior art solutions that have various disadvantages including lack of headroom, constrained operating characteristics, poor dynamics, and the need for controllable resistance devices (OTAs). What is needed then is a high-impedance current source which has a low compliance voltage, enhanced operating characteristics and dynamics, and which eliminates the need for OTAs.
SUMMARY OF THE INVENTION
These problems are generally solved, and technical advantages are generally achieved, by preferred embodiments of the present invention comprising a high impedance current source circuit having an enhanced compliance voltage. The current source circuit comprises an input circuit coupled to a first current mirror stage. A means for generating a biasing current produces a biasing current that is input into the input circuit. The first current mirror stage is in turn coupled to a second current mirror stage which acts as a feedback circuit. A stabilization circuit and output circuit which provides an output current are also included.
In one specific embodiment of the present invention, the first current mirror stage comprises a first transistor coupled to a second transistor; the second current mirror stage comprises a third transistor coupled to a fourth transistor; the stabilization circuit comprises a fifth transistor coupled to a sixth transistor, wherein the stabilization circuit is coupled between the first and second current mirror stages; and the output circuit comprises a seventh transistor connected to the stabilization circuit between the first and second current mirror stages.
The present invention also discloses a method for mirroring a current in the above embodiment of the present invention. The method comprises generating the biasing current; converting the biasing current into a gate voltage on the first, second, fifth, and sixth transistors; fixing the voltage across the fourth transistor whereby the percentage of current flowing through the sixth transistor and the fourth transistor is equal to the current flowing from the second transistor; and delivering a fixed current to the sixth and seventh transistors, whereby the voltage of said fifth transistor is substantially controlled to produce a stable output current.
An advantage of the preferred embodiment of the present invention is that the circuit has a low compliance voltage or point at which the circuit will operate. The low compliance voltage is due to the feedback operation included in the present invention. This low compliance voltage allows headroom for other circuitry operations.
Another advantage of the preferred embodiment of the present invention is that it is suitable for biasing wide common mode range differential pairs.
A further advantage of the preferred embodiment of the present invention is that the need for an active part or OTA is eliminated.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be desc
Bauduin Francois V. E.
Bonelli Andrea
Brady III W. James
Moore J. Dennis
Patel Rajnikant B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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