High gain pulse generator circuit with clock gating

Details High gain pulse generator circuit with clock gating High gain pulse generator circuit with clock gating

1997-12-31

2000-02-08

Nu Ton, My-Trang

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

327263, H03K 104, H03K 300

Patent

active

060231823

ABSTRACT:
A pulse generating circuit includes a first pulse generating circuit for generating a first output pulse, and a second pulse generating circuit for outputting a second output pulse. Each pulse generating circuit comprises a stack of two n-channel transistors and a reset circuit. The reset circuit includes two p-channel transistors and two inverters and is provided for automatically resetting the pulse generating circuits. The second pulse generating circuit includes a delay element for introducing an additional gate delay in the generation of the second output pulse. The additional gate delay introduces an asymmetry in the output pulses which offsets or cancels a previously introduced asymmetry of an input clock signal to generate an output clock signal having a constant period. Clock gating circuitry is provided for selectively enabling and disabling at least one of said pulse generator circuits.

REFERENCES:
patent: 5059818 (1991-10-01), Witt et al.
patent: 5243637 (1993-09-01), Flaherty et al.
patent: 5495194 (1996-02-01), Sugawara
patent: 5530387 (1996-06-01), Kim
patent: 5548235 (1996-08-01), Marbot
patent: 5586308 (1996-12-01), Hawkins et al.
patent: 5614841 (1997-03-01), Marbot et al.
patent: 5642068 (1997-06-01), Wojcicki et al.
patent: 5731724 (1998-03-01), Grishakov et al.

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