Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-02-15
2002-10-22
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S512000, C257S517000, C257S370000
Reexamination Certificate
active
06469362
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a bipolar junction transistor and, more particularly, to a high-gain pnp bipolar junction transistor in a CMOS circuit.
2. Description of the Related Art
Bipolar junction transistors (“BJTs”) are important in a number of applications in a CMOS device, which, by definition, includes at least one p-channel and one n-channel metal-oxide semiconductor field-effect transistor (“MOSFET”). BJTs generally exhibit higher gain, higher frequency performance and lower noise compared to MOSFETs. The gain (&bgr;) of a BJT is defined as the ratio of collector current I
C
over base current I
B
, and is inversely proportional to well-depth and well concentration. As a result, BJTs often exhibit lower than preferred gain when incorporated in a conventional CMOS circuit because of deep well-depth and high well concentration.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a high-gain pnp BJT in a CMOS device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawing.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided an integrated circuit device that includes a semiconductor substrate, a first n-well in the substrate, a first p-well contiguous with the first n-well in the substrate, and a second n-well contiguous with the first p-well. The second n-well includes a second p-well having a first n-type region and a second n-type region, wherein the first and the second n-type regions respectively define emitter and collector regions of a first BJT, a first p-type region spaced apart from the second n-type region, wherein the first p-type region and the second p-well respectively define emitter and collector regions of a second BJT, and a third n-type region spaced apart from the first p-type region.
In one aspect of the invention, the first n-type region is a collector of a composite pnp BJT.
In another aspect of the invention, the second p-well and the first p-type region comprise emitter of a composite pnp BJT.
In yet another aspect of the invention, the third n-type region is a base of a composite pnp BJT.
In still another aspect of the invention, the second p-well comprises an npn BJT.
In another aspect of the invention, the second p-well, the first p-type region, and the third n-type region comprise a pnp BJT.
Also in accordance with the invention, there is provided an integrated circuit device that includes a semiconductor substrate, an NMOS formed in the substrate, a PMOS contiguous with the NMOS and formed in the substrate, and a composite pnp bipolar junction transistor contiguous with the NMOS and formed in the substrate, wherein the composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having first and second spaced-apart n-type regions, and a lateral pnp bipolar junction transistor including the second spaced-apart n-type region, a first p-type spaced-apart region and a third n-type region, wherein the first p-type spaced-apart region and the third n-type region are separated by a shallow trench isolation.
In one aspect of the invention, a gain of the composite pnp bipolar junction transistor equals gain of the lateral npn bipolar junction transistor multiplied by a gain of the lateral pnp bipolar junction transistor.
Further in accordance with the present invention, there is provided an integrated circuit device that includes a semiconductor substrate, an NMOS formed in the substrate, a PMOS contiguous with the NMOS and formed in the substrate, and a composite pnp bipolar junction transistor contiguous with the NMOS and formed in SON the substrate, wherein the composite pnp bipolar junction transistor includes a lateral npn bipolar junction transistor having a first current gain, and a lateral pnp bipolar junction transistor having a second current gain, and wherein a current gain of the composite pnp bipolar junction transistor equals the first current gain multiplied by the second current gain.
Additionally in accordance with the present invention, there is provided a method for forming a composite pnp BJT in a CMOS device having a substrate including an n-well region. The method includes providing a first photoresist over the substrate, patterning and defining the photoresist to expose a portion above the n-well region, implanting the n-well region with a dopant to form a shallow p-well region, and removing the photoresist. The method also includes the steps of implanting a first dose of dopant to form lightly-doped n-type spaced-apart regions, implanting a second dose of dopant to form a lightly-doped p-type spaced-apart region, forming a gate structure including a gate and gate oxide, implanting a third dose of dopant into the lightly-doped spaced-apart n-type regions to form heavily-doped n-type regions wherein the third dose of dopant is more concentrated than the first dose of dopant, and implanting a fourth dose of dopant into the lightly-doped spaced-apart p-type region to form a heavily-doped p-type regions wherein the fourth dose of dopant has a higher concentration than the second dose of dopant.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4311532 (1982-01-01), Taylor
patent: 4642667 (1987-02-01), Magee
patent: 4760433 (1988-07-01), Young
patent: 5319235 (1994-06-01), Kihara
Yan et al., “Gate-Controlled Lateral PNP BJT: Characteristics, Modeling and Circuit Applications,” IEEE Transactions on Electron Devices (Jan. 1997) 44:118-128.
Wen Wen-Ying
Wong Shyh-Chyi
Chaudhuri Olik
Ha Nathan W.
Winbond Electronics Corp.
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