High gain, high speed, rail-to-rail amplifier

Amplifiers – With semiconductor amplifying device – Including differential amplifier

Reexamination Certificate

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Details

C330S255000

Reexamination Certificate

active

06326847

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention pertains to a high gain, high speed rail-to-rail amplifier, and more particularly to a high gain, high speed rail-to-rail amplifier that has two symmetrical input stages to provide amplification of input signals at the upper and lower ends of the input voltage range and to provide increased amplification of input signals in the middle voltage range. The high gain, high speed rail-to-rail amplifier of this invention is designed to be used in a variety of applications including scanners and other imaging devices.
2. Description of the Related Art
A conventional folded, cascode amplifier comprised of MOS transistors is shown in FIG.
1
. This amplifier
11
employs a single cascoded input stage comprised of two input transistors M
1
and M
2
which have their substrates coupled to supply voltage V
DD
. Input signals V
1
and V
2
(the difference of which represents a differential input signal &ugr;
IN
) are applied to the gates of M
1
and M
2
respectively. Current source transistor M
7
is biased by voltage V
BP
1
and generates a current, which is supplied to input transistors M
1
and M
2
.
Currents are drawn from the sources of input transistors M
1
and M
2
and are combined with currents drawn from the drains of transistors M
3
and M
4
which form part of the cascoded input stage and also act to amplify the input voltage signal. M
3
and M
4
, which have their substrates coupled to supply voltage V
SS
, have a common-gate connection to which a bias voltage V
BP
2
is applied. Transistors MS and M
6
form a current mirror that acts as a load for M
3
and M
4
.
Transistors M
3
and M
4
are provided with current source transistors M
10
and M
11
, each of which forms a current mirror with transistor M
14
. As a result of this connection, the current generated in the branch containing M
12
, M
13
and M
14
is induced in M
10
and M
11
to provide current for M
3
and M
4
. Voltages V
BP
1
and V
1
are applied to the gates of M
12
and M
13
respectively to generate the current in the M
12
, M
13
, M
14
branch.
The output stage, which is coupled to the cascoded input stage through a capacitor C
C
, includes transistor M
8
, the gate of which is driven by the voltage at the drain-drain connection between transistors M
4
and M
6
. A single-ended voltage output &ugr;
o
is taken off of the common drain connection between M
8
and a current source transistor M
9
which is biased by voltage V
BN
to generate current for the output stage.
One problem with the type of conventional amplifier shown in
FIG. 1
is that the single input stage is configured so that the magnitude of the differential input voltage signal &ugr;
IN
must be larger than V
T
(approx. 0.7 V) to turn the amplifier on. Thus, amplifier
11
is unable to provide any amplification of differential signals below this threshold.
Another problem with amplifier
11
is that it is unable to provide a full range output because of the configuration of the current source in the output stage. Having limited input and output ranges, amplifier
11
generates an output signal &ugr;
o
that does not follow &ugr;
IN
well at the low and high ends of the input range when amplifier
11
is used as a voltage follower. This ultimately leads to large distortion in the digital output signal produced by the scanner when amplifier
11
is employed in connection with an analog-to-digital converter in the scanner circuitry.
3. Objects of the Invention
Therefore, it is an object of this invention to overcome the aforementioned problems.
It is another object of this invention to provide a high gain, high speed rail-to-rail amplifier that generates an output signal which tracks the input signal very closely when used as a voltage follower, even at the high and low ends of the input voltage range.
It is a further object of this invention to provide a rail-to-rail amplifier having two symmetrical input stages, one that is responsive to input voltages in the low to middle ranges and the other that is responsive to input voltages in the middle to high ranges, and a gain stage which cooperates with the input stages to provide amplification of input voltages at the high and low ends of its range and to further increase the amplification of middle range input voltages.
It is still another object of this invention to provide a rail-to-rail amplifier having an output stage which is capable of generating a wide range of output voltages while efficiently controlling the current used for charging the load.
It is yet another object of this invention to provide a rail-to-rail amplifier having a selectively controlled power down circuit to reduce the current drawn from the power supply.
SUMMARY OF THE INVENTION
A rail-to-rail amplifier is provided for amplifying an electrical input signal. The amplifier comprises an n-input stage comprising a pair of input MOS transistors responsive to the electrical input signal when it is between a first middle value and a high value, a p-input stage comprising a pair of input MOS transistors responsive to the electrical input signal when it is between a low value and a second middle value higher than the first middle value, and a gain stage in electrical communication with each of the input stages to amplify the electrical input signal. In accordance with the invention, the gain stage receives an electrical signal from the n-input stage when the electrical input signal is between the first middle value and the high value, receives an electrical signal from the p-input stage when the electrical input signal is between the low value and the second middle value, and receives an electrical signal from both the n-input stage and the p-input stage when the magnitude of the electrical input signal is between the first middle value and the second middle value.
The rail-to-rail amplifier further comprises an output stage comprising a pair of output MOS transistors interconnected to form an output node where an electrical output signal is generated, a first MOS transistor responsive to a first control signal, and a second MOS transistor responsive to a second control signal, wherein the first and second MOS transistors cooperate to increase the output signal range and to provide the amplifier with increased driving ability.
The rail-to-rail amplifier may further include a power down circuit for placing the amplifier in a power down mode when no input signal is applied for some period of time. The power down circuit selectively turns on certain transistors and turns other transistors off to significantly decrease the amount of dc current drawn by the amplifier from the power supply.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.


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patent: 6066985 (2000-05-01), Xu
patent: 6100762 (2000-08-01), Kato
patent: 6107883 (2000-08-01), Xu

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