Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Substrate dicing
Reexamination Certificate
2002-10-28
2004-09-14
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Substrate dicing
C438S113000, C438S124000, C438S127000, C438S458000, C438S459000, C438S462000, C438S666000, C257S728000
Reexamination Certificate
active
06790694
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2002-240529 filed on Aug. 21, 2002; the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor module, a semiconductor device, and a manufacturing method of a semiconductor module. In particular, it relates to a manufacturing method that reduces the ground inductance of a high frequency circuit.
2. Description of the Related Art
Compound semiconductors such as a gallium arsenide (GaAs) and the like have superior characteristics including a favorable high-speed operation capability and a favorable power conversion efficiency as compared to silicon (Si). Development and implementation is progressing regarding a monolithic microwave integrated circuit (MMIC), an integrated high frequency circuit that utilizes such characteristics of compound semiconductors. A power amplifier module is a kind of MMIC that uses, for example, gallium arsenic hetero-junction bipolar transistors (HBT), and is widely used in equipment such as mobile phones. As the size of such equipment is reduced, demand has emerged for reducing the size of built in semiconductor devices therein. MMICs that meet these demands are being fabricated. However, the problem of parasitic impedance in ground wiring and the like may occur in reducing the size of semiconductor devices. In high frequency circuits, the parasitic impedance of wiring connecting the semiconductor device, and in particular ground wiring, affects the high frequency characteristic. For example, as shown in
FIG. 1
, the connection between a signal pad
112
and a ground pad
111
formed on a semiconductor device, and a signal line
107
and a ground
105
, respectively, on a mounting substrate
103
is implemented by bonding wires
118
a
and
118
b
. Since the ground connection between the semiconductor device on a semiconductor chip
121
and the mounting substrate
103
is made by the bonding wire
118
b
, ground inductance increases and the power gain of the power amplifier module deteriorates. In order to solve such problems regarding ground inductance, through-holes formed in the semiconductor substrate are used for the connection between the ground pad formed on a top surface of the semiconductor chip and the ground of the mounting substrate. With this method, after thinning semiconductor substrate, the through-holes are formed so as to pass through the semiconductor substrate from a bottom surface to the top surface, and a gold plating is formed on the entire area of the bottom surface of the semiconductor chip. It is thereby possible to make a ground connection without using wires, and ground inductance is drastically reduced. Nevertheless, this leads to a significant drop in yield since complicated processes are needed on a very thin semiconductor substrate, including a photolithography process on the bottom surface, an etching process to form the through-holes, and a plating process for the bottom surface. To avoid an etching process in forming the through-holes in a semiconductor substrate that already has been thinned, a proposed method includes, first forming through-holes in the top surface of the semiconductor substrate, forming a gold plated layer within each through-hole, polishing the bottom surface of the semiconductor substrate to expose the gold plated layer, and then forming a metal layer on the whole area of the bottom surface. However, with this method as well, the etching process to form the through-holes in the semiconductor substrate is necessary. Also, since process controlling in forming a cross-section of the through-holes appropriate for metallic filling is further required, complexity is not eliminated. Moreover, since individual chips are separated following formation of the metallic layer on the bottom surface of the thin semiconductor substrate, such a method causes yield to drop.
Thus the ground inductance may increase caused by the bonding wire with the earlier mounting configuration of high frequency semiconductor devices such as MMIC. In order to reduce the ground inductance, methods have been proposed to form the through-holes in a thin semiconductor substrate. However, a complicated process forming the through-holes or the like are required, in addition to regular fabrication processes for the semiconductor device.
SUMMARY OF THE INVENTION
A first aspect of the present invention inheres in a semiconductor module including: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.
A second aspect of the present invention inheres in a semiconductor device including: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element arranged on the top surface; and a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip.
A third aspect of the present invention inheres in a manufacturing method for a semiconductor module including: fabricating semiconductor elements and ground pads of the semiconductor elements, on a top surface of a semiconductor substrate; physically forming isolation trenches in isolation regions configured to divide the semiconductor substrate into a plurality of semiconductor chips; depositing a metal layer configured to connect to the ground pad and extend to the isolation trenches; separating the semiconductor substrate into the semiconductor chips at the isolation trenches by polishing a bottom surface of the semiconductor substrate across bottoms of the isolation trenches; disposing a conductive material to a ground metal arranged on a mounting substrate; and mounting one of the semiconductor chips on the conductive material configured to connect the metal layer with the ground metal with the conductive material.
REFERENCES:
patent: 6706547 (2004-03-01), Sakamoto et al.
patent: 5-47937 (1993-02-01), None
patent: 2606940 (1997-02-01), None
patent: 2634300 (1997-04-01), None
patent: 2001-308109 (2001-11-01), None
Kuriyama Yasuhiko
Morizuka Kouhei
Sugiura Masayuki
Sugiyama Toru
Tanabe Yoshikazu
Kabushiki Kaisha Toshiba
Wojciechowicz Edward
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