High-frequency semiconductor device and radio...

Telecommunications – Receiver or analog modulated signal frequency converter – With wave collector

Reexamination Certificate

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C455S127500, C455S083000, C257S728000, C257S723000, C257S724000, C257S604000, C333S247000

Reexamination Certificate

active

06366770

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high-frequency semiconductor devices and radio transmitter/receiver (transceiver) devices.
2. Description of the Related Art
Conventional high-frequency amplifiers for amplification of high-frequency signals at frequencies higher than or equal to 1 gigahertz (GHz) may include a transmitter amplifier adaptable for use in portable and mobile digital cellular radiotelephone terminals based on a currently available personal handy phone (PHP) system—in Japan the acronym “PHS” is more popular, so this acronym will be used hereinafter. An exemplary configuration of such a PHS terminal will be explained as follows.
In such high-frequency amplifiers, a source-grounded or “common-source” amplifier using GaAs metal semiconductor field effect transistors (MESFETs) has been typically employed today. The power gain per stage is approximately 10 decibels (dB), and the use of a serial combination of multiple—two to four—stages of such amplifiers permits the resultant circuitry to have an increased power gain ranging from 20 dB to 40 dB, more or less. This high-frequency amplifier is commercially available for use as a microwave monolithic integrated circuit (MMIC) in a growing electronics market. For reduction of cost penalties, MMICs are typically mounted or “embedded” in plastic packages, which are low-cost housings.
One prior art high-frequency semiconductor device designed for use as a MMIC is shown in FIG.
2
.
FIG. 2
is a diagram showing a plan view of a MMIC
10
having a high-frequency amplifier circuitry architecture in a four-stage configuration using four MESFETs with sources grounded, where the MMIC
10
is mounted to the frame of a plastic package. The MMIC
10
is put on a metallic plate
2
, called a “bed” among those skilled in the art to which the invention pertains.
The MMIC
10
is configured including FETs
12
1
, . . . ,
12
4
, matching circuits MC
1
to MC
4
, each of which consists of a capacitor and an inductor, and internal connection pads
14
a
to
14
1
,
14
n.
The semiconductor device also includes “external” pins
4
a-
4
n
along with bonding wires
20
a-
20
n.
Pins
4
g,
41
,
4
m
are connected to the bed
2
.
One matching circuit MC
1
has a capacitor MC
1
a
and an inductor MC
1
b
and is connected to pads
14
a,
14
h.
Another matching circuit MC
2
having a capacitor MC
2
a
and an inductor MC
2
b
is connected to a pad
14
i.
Another matching circuit MC
3
is formed of a capacitor MC
3
a
and inductor MC
3
b
and is coupled to a pad
14
j.
The remaining matching circuit MC
4
with a capacitor MC
4
a
and an inductor MC
4
b
is coupled to a pad
14
k.
On the other hand, an FET
12
1
at the initial stage (first-stage FET) has its gate connected to the matching circuit MC
1
and its drain connected to the matching circuit MC
2
with a source connected to the pad
14
b.
The second-stage FET
12
2
has a gate connected to the matching circuit MC
2
, a drain connected to the matching circuit MC
3
, and a source coupled to the pad
14
c.
The third-stage FET
12
3
has a gate connected to the matching circuit MC
3
with a drain coupled to the matching circuit MC
4
and with a source coupled to the pad
14
e.
The fourth-stage FET
12
4
has its gate connected to the matching circuit MC
4
and also coupled via a high resistance element to the pad
14
f,
a drain coupled to the pad
14
n,
and a source coupled to the pads
14
g,
141
. An output of the high-frequency semiconductor device is derived from the drain node of FET
124
, i.e. the pad
14
n.
The pads
14
a-
14
f
are connected by bonding wires
20
a-
20
f
to pins
4
a-
4
f,
respectively; pads
14
h-
14
k
are connected via bonding wires
20
h-
20
k
to pins
4
h-
4
k,
respectively. The pad
14
g
is connected to the bed
2
via three bonding wires
20
g,
pad
141
is coupled to bed
2
by four bonding wires
201
. As the bed is coupled to the grounded power supply in most cases, the pins
4
g,
41
,
4
m
are provided as GND-pins. The pad
14
n
is tied via the bonding wire
20
n
to the output pin
4
n.
Accordingly, pads
14
g,
141
, which are connected to the source of the final-stage FET
12
4
that is in closest proximity with the source side and thus suffers most significantly from a parasitic inductance problem, are directly connected by bonding wires to the bed
2
.
While the bed
2
is typically connected to more than one GND-pin in the way stated above, an inductance does exist at the GND-pins
4
g,
41
,
4
m
shown in
FIG. 2
, which results in the bed
2
not being set at the “ideal” GND in terms of high-frequency activities. Hereinafter, this GND which is potentially “floating” from the true GND at a certain impedance determinable in terms of high-frequencies will be referred to as a “virtual” GND.
An explanation will next be given of what kinds of problems can occur due to the presence of the virtual GND, rather than the ideal GND. While spiral inductors MC
1
b,
MC
2
b,
MC
3
b,
MC
4
b
are mounted on the MMIC
10
together with metal-insulator-metal (MIM) capacitors MC
1
a-
MC
4
a,
their layout areas are significant to the extent that they occupy a major part of a limited chip area. Hence, a coupling capacitance is present between these elements and the bed with a semiconductor substrate laid or “sandwiched” therebetween.
FIG. 3
is a pictorial representation of the semiconductor device structure to demonstrate how such extra capacitive components reside therein. As shown, a coupling capacitance Cp
1
exists between a circuit element
31
in MMIC
10
and its bed
2
whereas another coupling capacitance Cp
2
is between an element
32
and bed
2
. Because the bed
2
is potentially “floating” in terms of high frequencies as stated previously, the element
31
and element
32
are electrically coupled together via the capacitances Cp
1
, Cp
2
. Now, if it is assumed that the bed
2
is completely floating in potential from the true GND in the worst case, the element
31
and element
32
could be coupled together via a series-connected capacitor that is formed by the capacitance components Cp
1
and Cp
2
.
Such an undesirable capacitive coupling between or among certain elements on the MMIC
10
can result in a variety of kinds of malfunctions and operational failures. Especially, in multi-stage amplifier circuitry with a series combination or “cascade” connection of multiple FETs, the element-to-element capacitive coupling can result in serious problems, such as oscillation. An evaluation was done by the present inventors, described herein, which revealed that the most problematic issue lies in capacitive coupling between an input-side matching circuit of the N-th stage FET and an output-side matching circuit of its neighboring, (N+1) th stage FET (where, N is a natural number).
Suppose that an amplifier includes a serial combination of four stages of FETs as shown in FIG.
4
. As shown in
FIG. 4
, four matching circuits MC
1
, MC
2
, MC
3
, MC
4
are present between an input stage and output stage of such amplifier. Respective of the matching circuits is configured from a spiral inductor and an MIM capacitor, which can be capacitively coupled together through the bed
2
laid therebetween. For clarity purposes, consider the coupling between the matching circuits MC
1
, MC
3
only, which will be represented as a coupling capacitance Cf.
FIG. 5
shows the stability of the circuitry in
FIG. 4
, as obtained by simulation. An amplifier tested is of the class with a gain of 40 dB in the 1.9 GHz band. Supposing that the frequency in question as to the stability falls within a range of from 0.1 GHz to 10 GHz; then, it has been investigated how a minimal value (Kmin) of a stability factor K varies depending upon the feedback capacitance Cf in this frequency range. The result is shown in FIG.
5
. As is apparent from
FIG. 5
, when Cf goes beyond 13 femto-farads (fF), the value Kmin becomes less than 1 (i.e., Kmin<1) resulting in dissatisfaction of the absolute stability criteria

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