High frequency semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S752000, C257S753000, C257S275000, C257S276000, C257S296000, C361S310000, C361S437000, C361S437000, C361S794000, C361S792000, C438S167000, C438S186000

Reexamination Certificate

active

06747299

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a monolithic microwave integrated circuit (MMIC) in which a waveguide for high frequency signals is used. Each metallic signal line forming the waveguide must be disposed so as to be always integrated with the ground, because a high frequency signal is transmitted not in the line but between the line and the ground.
2. Description of the Related Art
In MMICs containing high speed semiconductor elements, such as high-electron-mobility transistors (HEMTs) and hetero-bipolar transistors (HBTs), a high frequency waveguide in which each signal line is integrated with the ground is needed for wiring so that a high frequency signal is transmitted, differently from ordinary silicon integrated circuits. A microstrip line which has stable line characteristics and weak dispersion characteristics which mean that frequency dependency of a transmission constant Is weak, is used as the high frequency waveguide.
In
FIG. 1
, among MMICs according to the related art in which microstrip lines used, in particular, a so-called “three-dimensional MMIC” having layers of line conductors is shown. In the three-dimensional MMIC in
FIG. 1
, a ground plate
3
is provided on a surface insulating layer
2
on the surface of a semiconductor substrate
1
. The ground plate
3
combines with line conductors
5
provided on insulating interlayers
4
to form microstrip lines.
The three-dimensional MMIC in
FIG. 1
has a superior feature in that the degree of integration is higher than that of a general type of MMIC having two-dimensionally formed layers.
Nevertheless, the three-dimensional MMIC in
FIG. 1
has a limitation in that, between each line conductor
5
and the ground plate
3
, another conductor cannot be disposed so as to two-dimensionally overlap with the line conductors
5
, because the conductor overlapping with the line conductor destroys the structures of the microstrip lines which are formed between each layer of line conductor
5
and the ground plate
3
. Accordingly, the three-dimensional MMIC in
FIG. 1
has limiting conditions stricter than those of an ordinary silicon integrated circuit.
SUMMARY OF THE INVENTION
As a result of considering conditions for a layout in an MMIC, the present inventor paid attention to layout limiting conditions, in particular, to a condition that the relationship between a power-supply conductor and each line conductor cannot be ignored. In other words, in the above MMIC, a power-supply conductor must be disposed between line conductors since each line conductor cannot be disposed overlapping with another conductor. The power-supply line greatly suppresses the degree of freedom in the arrangement of the line conductors since the lower limit of its width is determined for securing a predetermined current-carrying capacity, and it has a large area for its arrangement.
Accordingly, it is an object of the present invention to provide a three-dimensional MMIC having relaxed layout conditions.
To this end, according to the present invention, the above object is achieved through provision of a high frequency semiconductor device including a semiconductor substrate, a ground plate connected to the ground potential, a power-supply conductor which is provided above the ground plate, with insulating layer provided therebetween, and which is connected to a power-supply potential, and a line conductor provided above the semiconductor substrate, with an insulating interlayer. The line conductor combines with the ground plate or the power-supply conductor to form a high frequency transmission line, and the capacitance between the line conductor and one of the ground plate and the power-supply conductor is smaller than the capacitance between the ground plate and the power-supply conductor.
Preferably, the insulating layer is made of a material having a dielectric constant higher than that of the insulating interlayer.
The insulating layer may be made of material identical to that for the insulating interlayer, and may have a thickness smaller than that of the insulating interlayer.
A plurality of the line conductors may be provided as a plurality of layers, with the insulating interlayers provided therebetween.
The line conductor may be provided as a single layer in connection with the insulating interlayer.
The power-supply conductor may have a plane shape which is substantially identical to that of the ground plate.
The power-supply conductor may be provided in the form of a wiring line.
The power-supply conductor may be provided in the form of a plane on a selected area of surface of the semiconductor substrate.
The power-supply conductor may be provided in the form of a grid.
A plurality of the power-supply conductors may be provided as a plurality of layers each being electrically separated, with the insulating layers provided therebetween, and one of the power-supply conductors may be provided above the ground plate, with one of the insulating layers provided therebetween.
A plurality of the power-supply conductors may be provided, may be electrically separated from each other and may be two-dimensionally disposed on the semiconductor substrate.
A plurality of the ground plates may be disposed along the thickness direction of the semiconductor substrate, and the power-supply conductor may lie above at least one of the ground plates, with the insulating layer provided therebetween.
According to the present invention, a power-supply conductor and a line conductor can be disposed so as to overlap with each other, and the power-supply conductor can be disposed in a large area, so that the degree of freedom in an MMIC layout increases. In addition, the area of the entire semiconductor chip can be reduced because the power-supply conductor and the line conductor overlap with each other two-dimensionally.


REFERENCES:
patent: 4739448 (1988-04-01), Rowe et al.
patent: 4789809 (1988-12-01), Christensen
patent: 5272600 (1993-12-01), Carey
patent: 5354599 (1994-10-01), McClanahan et al.
patent: 5384486 (1995-01-01), Konno
patent: 5396397 (1995-03-01), McClanahan et al.
patent: 5402318 (1995-03-01), Otsuka et al.
patent: 5519176 (1996-05-01), Goodman et al.
patent: 5854534 (1998-12-01), Beilin et al.
patent: 6002593 (1999-12-01), Tohya et al.
patent: 6075211 (2000-06-01), Tohya et al.
patent: 6225958 (2001-05-01), Amano et al.
patent: 63-052466 (1988-03-01), None
patent: 07-307567 (1995-11-01), None
patent: 08-162621 (1996-06-01), None
patent: 2000-269429 (2000-09-01), None
Office action and translation dated May 20, 2003 from the corresponding Japanese application.

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