Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For high frequency device
Reexamination Certificate
2002-03-06
2004-08-10
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For high frequency device
C257S758000
Reexamination Certificate
active
06774484
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high-frequency monolithic microwave integrated circuits (MMICs), and in particular, to an MMIC which supplies a high power output.
Many high-frequency MMICs include a semiconductor chip having a transistor which needs a DC bias. To obtain large output power, a large current must be supplied to the transistor. The present invention provides a multilayer wiring structure provided on a semiconductor substrate in order to supply a DC bias to the transistor.
2. Description of the Related Art
FIGS. 1A and 1B
illustrate a semiconductor device according to the related art.
FIGS. 1A and 1B
are cross-section and plan views of the multilayer wiring structure of the semiconductor device, respectively.
As shown in
FIGS. 1A and 1B
, the semiconductor device has a multilayer wiring structure in which an insulating layer
2
and multilayer wiring layers (no intermediate layer shown) are stacked on a semiconductor substrate
1
. DC power is externally supplied to a power-supply pad
9
provided on the top of the multilayer wiring structure via a wire or the like. In the semiconductor device, from a power-supply line
4
which connects to the power-supply pad
9
and extends on the semiconductor substrate
1
, a power-supply potential is supplied to an active region
3
formed on the semiconductor substrate
1
, for example, to a transistor's drain
6
via throughholes
5
.
For a high frequency MMIC, a power-supply circuit must be designed not as a simple DC-power-supply circuit but as a distributed constant circuit having low-pass-filter characteristics. Consequently, a power-supply-wiring layout has limiting conditions which are characteristic in a high frequency circuit. Accordingly, a high degree of freedom in the layout is greatly demanded.
To obtain large output power, a large current must be supplied to the transistor. Thus, a power-supply line must have a predetermined width in order to secure a current-carrying capacity. When the power-supply line does not satisfy the predetermined width, problems occur, such as a voltage drop caused by the resistance of the power-supply line, heat generated by the power-supply wiring, and migration in the power-supply wiring.
For the high frequency MMIC, the power-supply wiring is normally designed as a distributed constat circuit which does not allow a high frequency signal to pass through it. In order that the distributed constant circuit may not allow the high frequency signal to pass through it, a wiring length which is approximately a quarter of the wavelength of the signal is required. Also, when wiring lines are arranged so as to be mutually close, unexpected coupling is generated between lines, and the arrangement is not preferable for a circuit. Accordingly, the wiring must be performed so that lines are disposed at intervals. Regarding the wiring interval, in the case of a microstrip line which is commonly used in the MMIC, the microstrip line cannot fulfill its function unless the writing interval is increased to be larger than a distance up to the ground on the back of a semiconductor chip.
Therefore, to obtain high output, power-supply lines which each have a length larger than the quarter wavelength and a large width must be disposed, with a distance provided between two lines. The thus formed wide and long power-supply circuit reduces the degree of freedom in the chip layout and leads to an increase in the area of the semiconductor chip.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a multilayer wiring structure for semiconductor devices in which the degree of freedom in the layout of wiring is increased.
To this end, according to the present invention, the above object is achieved through provision of a multilayer wiring structure for semiconductor devices which includes a semiconductor substrate, at least one active region supplied with an electric power from a power-supply potential, and a plurality of power-supply lines for supplying with the electric power to said active region therethrough, which are disposed at different layers of the multilayer wiring structure on said semiconductor substrate and are connected in parallel to each other.
Preferably, a common power-supply line which is connected to the power-supply lines and which has a current-carrying capacity larger than that of each of the power-supply lines is provided between the power-supply potential and the at least one active region.
The multilayer wiring structure may further include at least one power-supply pad connecting to the power-supply potential. The common power-supply line may be provided between the power-supply pad and the power-supply lines.
The common power-supply line may be provided between the active region and the power-supply lines.
The common power-supply line may be provided between the power-supply potential and the at the active region, with both ends thereof connecting to the power-supply lines.
The power-supply lines may connect in parallel to the active regions.
The power-supply lines may connect to the power-supply potential by a plurality of power-supply pads connecting in parallel to the power-supply lines.
According to the present invention, the width of each power-supply line can be reduced, so that the area of a semiconductor chip is reduced and the degree of freedom in the layout of wiring for design of a high-frequency semiconductor device is increased. This greatly contributes to an improvement in the performance of the semiconductor device.
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Office Action dated May 13, 2003 from Japanese Patent Office in corresponding Japanese patent application and English translation.
Ali M. Niknejad and Robert G. Meyer: “Analysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's”, IEEE Journal of Solid-State Circuits, vol. 33, No. 10, Oct. 1998.
Aoki Yoshio
Baba Osamu
Gotoh Muneharu
Mimino Yutaka
Fujitsu Quantum Devices Limited
Ho Tu-Tu
Westerman Hattori Daniels & Adrian LLP
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