Amplifiers – With control of power supply or bias voltage – With control of input electrode or gain control electrode bias
Reexamination Certificate
2001-09-25
2004-05-04
Tokar, Michael (Department: 2819)
Amplifiers
With control of power supply or bias voltage
With control of input electrode or gain control electrode bias
C330S133000, C330S285000
Reexamination Certificate
active
06731167
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high frequency power amplifier having a pluralty of amplifying systems and a wireless communication apparatus including the high frequency power amplifier, and particularly relates to a technology usefully applicable to a multi-band communication type of cellular phone which has multiple communication functions of different communication frequencies.
2. Prior Art
In North American cellular phone market, so-called dual mode cellular phones have recently been spreading which are cellular phones incorporating conventional analog AMPS (advanced mobile phone services) that cover the whole of the North America and digital services such as TDMA (time division multiple access) and CDMA (code division multiple access).
In other regions including Europe, GSM (Global system for mobile communication and DCS (digital cellular system) utilizing TDMA techniques and FDD (frequency division duplex) techniques are used.
In “Nikkei Electronics” pp. 140-153 published by Nikkei BP Corp. on Jul. 26, 1999 [No. 748], a dual mode cellular phone was disclosed in which a GSM having an operating frequency of 800 to 900 MHz and a DCS having an operating frequency of 1.7 to 1.8 GHz are integrated. The same article disclosed a multi-layer ceramics device in which passive components are integrated to make the circuit as a whole compact.
Further, a dual band RF power module was disclosed in “GAIN” No. 131, January 2000 published by Semiconductor Group of Hitachi, Ltd.
SUMMARY OF THE INVENTION
There is a trend toward cellular phones with increased functions to allow advanced information communication. High frequency power amplifiers (high frequency power amplifier modules) incorporated in cellular phones have more functions to satisfy such a need. Especially, high frequency power amplifiers having a plurality of communication modes (and communication bands) are assembled from a greater number of components compared to single communication mode products, which increases the size and cost of such devices.
Under such circumstances, the inventors studied the possibility of a reduction in the number of chip resistors incorporated in a high frequency power amplifier in order to provide the amplifier with smaller outline dimensions.
FIG. 23
is a circuit diagram showing the relationship between an equivalent circuit of a conventional dual band type high frequency power amplifier module incorporating a GSM and a DCS and semiconductor chips and the like. The high frequency power amplifier module has an amplifying system e for GSM as a first amplifying system and an amplifying system f for DCS as a second amplifying system.
The GSM amplifying system e has a three-stage consisting configuration (consisting of a first amplifying stage, a second amplifying stage, and a third amplifying stage (final amplifying stage)) in which transistors Q
1
, Q
2
, and Q
3
are sequentially cascaded between an input terminal Pin-GSM and an output terminal Pout-GSM.
Each of the transistors Q
1
, Q
2
and Q
3
is constituted by a MOSFET (metal oxide semiconductor field-effect-transistors) and is applied with a signal and a bias potential at its gate electrode which is a control terminal. The bias potential is applied to a bias terminal Vapc-GSM (or automatic power control terminal), and a predetermined bias potential is applied to the respective control terminal through bias resistors R
1
through R
5
.
A power supply potential Vdd-GSM is applied to a first terminal (drain terminal) of each of the transistors Q
1
, Q
2
, and Q
3
, and an amplification signal is output to the first terminal. A reference potential (ground potential) is supplied to a second terminal (source electrode) of the transistors. L
1
through L
7
represent a matching circuit.
The DCS amplifying system f has the same configuration as that of the above-described GSM amplifying system e. Specifically, it has a three-stage configuration (consisting of a first amplifying stage, a second amplifying stage, and a third amplifying stage (final amplifying stage)) in which transistors Q
4
, Q
5
, and Q
6
are sequentially cascaded between an input terminal Pin-DCS and an out put terminal Pout-DCS.
Each of the transistors Q
4
, Q
5
and Q
6
is constituted by a MOSFET and is applied with a signal and a bias potential at its gate electrode which is a control terminal. The bias potential is applied to a bias terminal Vapc-DCS, and a predetermined bias potential is applied to the respective control terminal through bias resistors R
6
through R
10
.
A power supply potential Vdd-DCS is applied to a first terminal (drain terminal) of each of the transistors Q
4
, Q
5
, and Q
6
, and an amplification signal is output to the first terminal. A reference potential (ground potential) is supplied to a second terminal (source electrode) of the transistors. L
8
through L
14
represent a matching circuit.
The transistors Q
1
and Q
2
of the GSM amplifying system e and DCS amplifying system f have a monolithic configuration in that they are incorporated in a single semiconductor chip. In such a configuration, however, bias resistors are externally mounted, which hinders reduction of the size of high frequency power amplifiers. Further, while the first and second amplifying stages of both the GSM amplifying system e and DCS amplifying system f are integrated in one semiconductor chip, two semiconductor chips are required because there are two amplifying systems, which also hinders reduction of the size of high frequency power amplifiers.
Referring to the transistors that constitute the amplifying stage, since the threshold voltage Vth of the transistors is slightly inconsistent (varies) between production lots, the bias resistance ratios of the resistors that form a bias circuit must be changed from lot to lot. This method makes manufacturing operations complicated because chip resistors must be selected for use in each production lot.
It is an object of the invention to provide a compact high frequency power amplifier and a wireless communication apparatus incorporating the same high frequency power amplifier.
It is another object of the invention to provide a technique for allowing a bias resistance ratio to be easily adjusted in accordance with a change in a threshold voltage Vth of a transistor.
The above and other objects and novel features of the invention will become apparent from the description of the present specification and the accompanying drawings.
Briefly, primary aspects of the invention disclosed in this specification are as follows.
(1) There is provided a high frequency power
amplifier having a plurality of amplifying systems, characterized in that each of the amplifying systems comprises:
an input terminal to which a signal to be amplified is supplied;
an output terminal;
a bias terminal;
a plurality of amplifying stages which are sequentially cascaded between the input terminal and output terminal; and
a bias circuit connected to the bias terminal and each of the amplifying stages to apply a bias potential to the amplifying stage, in that each of the amplifying stages includes a control terminal for receiving an input signal and the bias potential supplied to the stage and a first terminal for transmitting an output signal of the stage, and in that a first amplifying stage and a second amplifying stage of each of the amplifying systems are monolithically formed on a single semiconductor chip, and a part of bias resistors that constitute bias circuits of the first amplifying stage and second amplifying stage are monolithically formed on the semiconductor chip.
Referring to the terminals of the first amplifying stage and second amplifying stage provided on a surface of the semiconductor chip, the control terminals and the first terminals are alternately provided in the same direction.
A wire that is connected to the control terminal of the second amplifying stage provided on the surface of the semiconductor chip and a wire connected to the first terminal of the second amplifyi
Adachi Tetsuaki
Akamine Hitoshi
Maruyama Masashi
Sato Takahiro
Suzuki Masashi
Mattingly Stanger & Malur, P.C.
Nguyen Linh Van
Renesas Technology Corp.
Tokar Michael
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