Amplifiers – With semiconductor amplifying device – Including gain control means
Reexamination Certificate
2002-05-17
2004-06-29
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including gain control means
C330S288000
Reexamination Certificate
active
06756850
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a multi-stage high-frequency power amplifier circuit with a plurality of cascaded semiconductor amplifier devices and technology that is useful when applied to wireless communication devices such as cellular phones incorporating a high-frequency power amplifier circuit, and more particularly to a high-frequency power amplifier circuit capable of obtaining output with desired characteristics, independent of variations in semiconductor amplifier device characteristics.
The transmission output stage of car phones, cellular phones, and other wireless communication devices (mobile communication devices), as shown in
FIG. 1
, includes a multi-stage high-frequency power amplifier circuit with cascaded semiconductor amplifier devices Q
1
, Q
2
, and Q
3
made of MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), GaAs-MESFETs (Metal Semiconductor Field-Effect Transistors), or other applicable kinds of transistors. The high-frequency power amplifier circuit shown in
FIG. 1
generally includes a discrete last-stage semiconductor amplifier device Q
3
(such as an output power MOSFET), and preceding-stage semiconductor amplifier devices Q
1
and Q
2
and a bias circuit BIAS that are integrated onto a single semiconductor chip as a semiconductor integrated circuit. The combination of this discrete semiconductor amplifier device part and a semiconductor integrated circuit including a bias circuit, together with capacitive elements and other circuit elements will be referred to as a high-frequency power amplifier module or just as a module hereinafter.
In general, a cellular phone system is configured to change its output (transmission power) in different communication environments according to power-level command signals from a base station, so as not to interfere with other cellular phones. For example, a high-frequency power amplifier module in the transmission output stage of cellular phones adopting the U.S. 900-MHz band standard system or the European GSM (Global System for Mobile Communications) system is configured so that the gate bias voltages of the output power MOSFETs Q
1
to Q
3
are controlled by the output voltage Vapc of an Automatic Power Control (APC) to produce the output power required for communication.
Conventionally, the gate bias voltages of the output power MOSFETs are generated by using a bias circuit BIAS consisting of resistance dividers as shown in
FIG. 1
, in which the output voltage Vapc of the APC circuit is divided by the ratios of paired resistances R
11
and R
12
, R
21
and R
22
, and R
31
and R
32
to generate gate bias voltages Vg1, Vg2, and Vg3 (see, for example, Unexamined Japanese Patent Publication No. Hei 11(1999)-150483).
Some conventional systems, as shown in
FIG. 2
, use a bias circuit that is configured with a plurality of resistances R
1
to R
4
connected in series with a MOSFET Qd that functions as a diode, forming a resistive voltage in which the ratio of the resistance values is adjusted so that the maximum output power can be obtained when Vapc is in the high neighborhood of 2 V, generating the gate bias voltages Vg1, Vg2, and Vg3 of the output power MOSFETs in each stage (see, for example, Unexamined Japanese Patent Publication No. 2001-102881).
As described above, all of the conventional gate bias circuits above apply bias voltages generated by dividing the output voltage Vapc of the APC circuit to the gates of the output power MOSFETs.
SUMMARY OF THE INVENTION
Output power MOSFETs show variations in threshold voltages due to manufacturing process variations and temperature changes. In addition, the last-stage MOSFET Q
3
among the output power MOSFETs, in particular, is often a discrete part. Therefore, the last-stage MOSFET Q
3
and preceding-stage MOSFETs Q
1
and Q
2
differ in regard to the variations in the threshold voltage. More specifically, the gate voltage-drain current characteristics of the output power MOSFETs are different from each other.
In such a high-frequency power amplifier module configured with output power MOSFETs having different variations in their threshold voltages, if a gate bias voltage that is generated by dividing the output voltage Vapc of the APC circuit according to the ratio of resistances is applied to the gate terminals of the output power MOSFETs, the output characteristic of the high-frequency power amplifier circuit may deviate greatly from a desired characteristic. As a result, a module with a bias circuit that generates gate bias voltage by dividing resistances requires fine tuning of the resistance values making up the bias circuit; this obviously creates a problem in that extra trimming tasks or trimming resistors are required.
Accordingly, an object of the present invention is to provide a high-frequency power amplifier circuit capable of obtaining desired characteristics without trimming the values of resistors making up the bias circuit.
Another object of the present invention is to provide a high-frequency power amplifier circuit with better output controllability.
Another object of the present invention is to provide a high-frequency power amplifier circuit capable of efficiently obtaining higher output with lower power consumption.
The aforementioned and other objects and new features of the present invention will become clear from the description in this specification when read with reference to the attached drawings.
The outline of a typical mode of practicing the invention disclosed herein will be described below.
In a multi-stage high-frequency power amplifier circuit with a plurality of cascaded output semiconductor amplifier devices Q
1
, Q
2
, and Q
3
, the invention typically provides semiconductor amplifier devices Q
11
, Q
12
, and Q
13
connected to the plurality of output semiconductor amplifier devices to form current mirror circuits respectively, causing electric currents I11, I12, and I13 changing with given characteristics according to control voltage to flow into the semiconductor amplifier devices and driving the plurality of output semiconductor amplifier devices with the currents.
The method described above drives the output semiconductor amplifier devices with currents having given characteristics, thereby making it possible to obtain a high-frequency power amplifier circuit with output characteristics not sensitive to possible variations in the threshold voltages and other characteristics of the output semiconductor amplifier devices.
The semiconductor amplifier devices are preferably field effect transistors, and the given characteristics are their gate voltage-drain current characteristics. Since the drain current of a field effect transistor is proportional to the square of the gate voltage, the control voltage can reduce the rate of change of the output in the vicinity of the threshold voltage of the field effect transistor and increase the rate of change of the output by increasing itself, thereby making it possible to achieve higher output controllability and larger output power.
According to another aspect of the invention disclosed herein, in a high-frequency power amplifier circuit having a multi-stage output circuit with a plurality of cascaded semiconductor amplifier devices Q
1
, Q
2
, and Q
3
and a bias circuit that drives the semiconductor amplifier devices responsive to a control voltage, the invention provides semiconductor amplifier devices Q
11
, Q
12
, and Q
13
that are connected to the plurality of output semiconductor amplifier devices so as to form current mirror circuits; the bias circuit has a voltage-to-current converter
10
, a first resistance R
1
that converts currents I1 and I3 supplied from the voltage-to-current converter, a first constant-current source
31
, and a first semiconductor amplifier device Q
32
connected in series thereto; also included is a control voltage generator
30
that generates a voltage equal to the threshold voltage of the first semiconductor amplifier device; a second semiconductor amplifier device Q
21
(Q
31
) generates current
Furuya Tomio
Matsudaira Nobuhiro
Matsushita Kouichi
Morisawa Fuminori
Tsutsui Takayuki
Choe Henry
Mattingly Stanger & Malur, P.C.
Renesas Technology Corp.
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