High frequency phase-locked loop circuit having reduced jitter

Details High frequency phase-locked loop circuit having reduced jitter High frequency phase-locked loop circuit having reduced jitter

1997-10-03

1999-02-09

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 8, 331 25, 331 34, 331 57, 327157, H03L 7089, H03L 718

Patent

active

058700030

ABSTRACT:
A phase-locked loop circuit for providing external clock signals to a processor is disclosed. The phase-locked loop circuit includes a phase/frequency detector, a voltage-control oscillator, and two charge pumps. The phase/frequency detector receives an input reference signal and provides a first differential output and a second differential output. The voltage-controlled oscillator has a feed-forward current input and is utilized to generate an output clock signal, wherein the output clock signal is also utilized as a feedback signal for the phase/frequency detector. The first charge-pump, coupled between the phase/frequency detector and the voltage-controlled oscillator, receives the first and second differential outputs from the phase/frequency detector and provides a differential voltage control signal for the voltage-controlled oscillator. The second charge pump is utilized to produce a stable system response by increasing the loop dumping.

REFERENCES:
patent: 5740213 (1998-04-01), Dreyer

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