Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2001-09-28
2004-05-18
Wong, Edna (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S105000, C205S157000, C205S118000, C205S123000
Reexamination Certificate
active
06736953
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to a method of depositing one or more conductive layers as part of a very large scale integrated circuit using a high frequency pulse reverse electrochemical deposition technique.
BACKGROUND
As integrated circuits become more complex, it becomes necessary to develop new structures and fabrication techniques to reduce the overall size of the integrated circuits. One technique for reducing the physical size of an integrated circuit is to form multi layered structures where metallic interconnects, separated by interlevel dielectric layers, overlay one another to define various electrical pathways. As the size of the circuit is reduced, electrical contacts, via holes and other structures are typically made smaller and located in closer proximity to one another.
Metallic layers are often deposited to form electrical interconnects. One typical deposition process is low frequency pulse reverse plating. Low frequency pulse reverse plating has a number of associated drawbacks that tend to diminish the operation of the integrated circuit. Trenches, such as vias, trenches, and dual damascene structures that are fabricated with low frequency pulse reverse plating tend to have defects such as voids, irregular surface profiles and impurities. These defects tend to inhibit the proper operation of the integrated circuits manufactured according to these methods, resulting in an associated reduction in the device yield achieved during the manufacturing process.
As the trend toward fabrication of devices having smaller feature sizes and higher performance continues, there are increasing incentives to avoid the fabrication problems such as described above. The development and use of improved processing techniques can achieve both better device performance, and minimize production costs by improving the device yield during manufacturing.
What is needed, therefore, is a method for processing a substrate to form trenches, which method tends to improve the performance characteristics and device yield of the integrated circuits.
SUMMARY
The above and other needs are met by a method of forming an electrically conductive structure on a substrate. An electrically conductive electrode layer is formed on the substrate, and an electrically conductive conduction layer is formed over the electrode layer. The conduction layer is formed by placing the substrate in a plating solution. A first current is applied to the substrate at a first bias and a first density for a first duration. A second current is applied to the substrate at a second bias and a second density for a second duration. The first current and the second current are cyclically applied at a frequency of between about thirty hertz and about one hundred and thirty hertz.
In various preferred embodiments the density of the second current is between about two times and about four times the density of the first current. Most preferably the first bias is a forward bias and the second bias is a reverse bias. The first duration is preferably between about four and about twenty milliseconds, most preferably corresponding to a depletion time of the plating solution, and the second duration is preferably between about one and about four milliseconds, most preferably corresponding to a replenishment time of the plating solution.
By cycling the forward bias and the reverse bias in the plating solution for the durations and current densities described above, and at the frequency described above, a layer of material is deposited on the substrate that exhibits a reduced amount of defects, such as voids and impurities. Without being bound to theory, the reduction in voids and the reduction in impurities may be attributed to the relatively short forward bias time, which tends to allow the desired reactants in the plating solution sufficient time to transport to the reaction sites on the substrate, and thus reduces both the amount of impurities that are deposited onto the substrate out of the plating solution and the amount of unwanted byproduct gasses that are produced during those times when the desired reactants are depleted. Another purpose of the reverse bias is to etch the metallic deposition at the comers of trench or via openings. Deposition at the comers will block the deposition inside the features and is the one of the main reasons that voids are formed.
In an alternate embodiment of the method for forming an electrically conductive structure on a substrate, an etched feature is formed in the substrate. An electrically conductive electrode layer is formed on the substrate, and an electrically conductive conduction layer is formed on the electrode layer. The conduction layer is formed by placing the substrate in a plating solution. A first current is applied to the substrate at a first bias and a first density for a first duration, where the first duration corresponds to a depletion time of the plating solution in the etched feature. A second current is applied to the substrate at a second bias and a second density for a second duration, where the second duration corresponds to a replenishment time of the plating solution in the etched feature.
The second current tends to etch the substrate and keep the top of the features on the substrate open for that period of time before they are completely filled with the material of the conduction layer. Once the features are filled with the material of the conduction layer, the function of the second current is, at least in part, to prevent the conduction layer from over growing on top of the features, which tends to produce a flat surface instead of a dome shaped surface. Therefore, either the density of the second current, or the duration of the current may need to change after the features are filled. A dead time is applied where no current is applied to the substrate. The first current, second current, and dead time are cyclically applied at a frequency of between about thirty hertz and about one hundred and thirty hertz.
According to another aspect of the invention, an integrated circuit is described, where the improvement is an electrically conductive structure formed according to one or more of the methods described above.
REFERENCES:
patent: 6303014 (2001-10-01), Taylor et al.
patent: 6432821 (2002-08-01), Dubin et al.
patent: 6440289 (2002-08-01), Woo et al.
S. Gandikota, et al., “Extension of Copper Plating to 0.13 micron Nodes by-Pulse-Modulated Plating,” Proceedings of The International Interconnect Technology Conference, California, Jun. 2000.
Wang Zhihai
Zhu Mei
LSI Logic Corporation
Luedeka Neely & Graham
Wong Edna
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