High frequency differential receiver

Details High frequency differential receiver High frequency differential receiver

2001-02-20

2002-06-18

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S052000

Reexamination Certificate

active

06407590

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to differential receivers.
BACKGROUND OF THE INVENTION
The input stage of a prior art small swing differential receiver has been implemented as shown in FIG.
1
. The differential receiver of
FIG. 1
contains three P-channel transistors
20
,
22
, and
24
, and four N-channel transistors
26
,
28
,
30
, and
32
. Another circuit supplies the bias voltage to the gate of transistor
20
. Then transistor
20
acts as a current source which is tied to a differential pair formed by transistors
22
and
24
. When input node
34
is lower in voltage than input node
36
, a majority of the current supplied by transistor
20
is steered through transistor
22
, with the remainder of this current flowing through transistor
24
. In order to insure that a large enough signal swing is generated at output nodes
38
and
40
, cross-coupled transistors
26
and
28
are added, which gives this circuit additional gain. However, adding transistors
26
and
28
can cause the signal swing to become too large under some conditions, so clamp transistors
30
and
32
are added.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, the differential receiver circuit includes: a current source; a differential pair coupled to the current source; a first transistor coupled to a first branch of the differential pair; a second transistor coupled to a second branch of the differential pair, the first and second transistors are cross coupled; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the second transistor; a fifth transistor coupled in parallel with the first and third transistors; and a sixth transistor coupled in parallel with the second and fourth transistors.


REFERENCES:
patent: 4521703 (1985-06-01), Dingwall
patent: 4606012 (1986-08-01), Koshizuka
patent: 4616148 (1986-10-01), Ochii et al.
patent: 5977798 (1999-11-01), Zerbe
patent: 6147514 (2000-11-01), Shiratake

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