High frequency CMOS clock recovery circuit

Details High frequency CMOS clock recovery circuit High frequency CMOS clock recovery circuit

1998-08-27

2000-09-19

Zweizig, Jeffrey

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327155, 327166, H03L 700

Patent

active

061218049

ABSTRACT:
A complementary metal-oxide semiconductor (CMOS) integrated circuit that includes a clock recovery circuit. The clock recovery circuit automatically properly aligns a clock with data. A latch is used to perform the function of a flip-flop. Because the flip flop is essentially two latches, using the latch rather than the flip flop results in a circuit having one less latch. Consequently, the circuit has less propagation delay, which permits higher frequency operation. Use of the latch also reduces the load on the clock and saves power. Additionally, the clock recovery circuit uses differential logic, which decreases noise sensitivity and allows higher frequency operation.

REFERENCES:
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 5619171 (1997-04-01), Rijckaert et al.
patent: 5770976 (1998-06-01), Nagaraj
patent: 5799048 (1998-08-01), Farjad-Rad et al.
C. Hogge, Jr., "A Self Correcting Clock Recovery Circuit," J. of Lightwave Technology, vol. LT-3, No. 6, Dec. 1985.
M. Park et al., "Novel Regenerator Having Simple Clock Entration and Automatic Phase-Controlled Retiming Circuit," Journal is unknown, Jul., 1988; Authors from Optical Communications Section, Electronics & Telecommunications Research Institute, Chungnam, Korea.
T. Wong et al., "A 10Gb/s ATM Data Synchronizer," IEEE J. of Solid-State Circuits, vol. 31, No. 10, Oct. 1996.

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