Telecommunications – Transmitter – Power control – power supply – or bias voltage supply
Reexamination Certificate
2001-04-05
2004-10-12
Nguyen, Duc M. (Department: 2685)
Telecommunications
Transmitter
Power control, power supply, or bias voltage supply
C455S127200, C455S127300, C455S245200, C455S251100, C455S250100, C330S295000, C330S051000, C330S12400D
Reexamination Certificate
active
06804500
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high frequency circuit for realizing a high efficiency power amplifier with a wide output power range which is suitable for use in a portable telephone or the like, for example, and a communication device using such a high frequency circuit.
2. Description of the Related Art
In general, the power amplifier has an efficiency which lowers at low output, because its power addition efficiency increases as the output power is increased and takes the maximum value in a vicinity of the saturation point of the output power.
FIG. 1A
shows an exemplary relationship between the efficiency and the output power at low output in a general amplifier. Here, the efficiency is a value obtained by dividing an RF (high output) output power by a DC (direct current) input power, which corresponds to a collector efficiency of a bipolar transistor and a drain efficiency of a field effect transistor.
FIG. 1B
shows an inverse of the efficiency shown in
FIG. 1A
in the logarithmic scale.
As shown in
FIGS. 1A and 1B
, the efficiency is sequentially degraded from 72% at the output power of 30 dBm (dBmW to be accurate, but will be abbreviated as dBm hereafter) to 21.8% at the output power of 20 dBm, 4.7% at the output of 10 dBm, and 1,5% at the output power of 5 dBm. Accordingly, a ratio of the DC input power with respect to the RF output power sequentially increases to 1.4 at the 30 dBm output, 4.6 at the 20 dBm output, 21.2 at the 10 dBm output, and 67.1 at the 5 dBm output.
The cause of this degradation of the efficiency at low output will now be explained using a simplified ideal transistor model.
FIGS. 2A and 2B
show graphs indicating a relationship between current and voltage in the alternating currents.
In
FIGS. 2A and 2B
, it is assumed that a load line is as indicated by a chain line KB, the output voltage is in a form of a sinusoidal wave with an average value set at a bias voltage, and the output current is in a form of a half-wave rectified wave Iout(t). Note that a point B in
FIGS. 2A and 2B
corresponds to the bias point.
FIGS. 2A and 2B
show the case of the class B operation. The RF output power is given by a product of an effective value of the fundamental wave component Vout of the output power and an effective value of the fundamental wave component I
1
(t). One half of an area of a rectangle with a point R and a point B as diagonal corners corresponds to the RF output power.
The DC input power is given by a product of the bias and an average value of the output current Iout(t), which corresponds to an area of a rectangle with a point D and a point B as diagonal corners (which will be referred to as a rectangle DB hereafter) in
FIGS. 2A and 2B
. The efficiency is given by a ratio of these two areas.
With respect to the case of
FIG. 2A
, in the case of
FIG. 2B
, the current amplitude and the voltage amplitude are both reduced to ½ so that the output power is ¼. On the other hand, the direct current is given by an average value of the RF current so that it is also reduced to ½ but the direct current voltage is fixed at a point B, so that the area of the rectangle DB is ½. As a result, the efficiency is reduced to ½ whenever the RF output power is reduced to ¼ (−6 dB). In practice, a rate of the degradation of the efficiency is greater than ½ due to the influence of the knee voltage or the fact that the operation is actually the class AB operation.
Conventionally, one way of compensating such a degradation of the efficiency at low output is to use an amplifier circuit as shown in FIG.
3
A.
Namely, as shown in
FIG. 3A
, in this conventional amplifier circuit, a plurality of amplifiers with different maximum output powers, AMP
1
(with maximum output of −20 dBm) AMP
2
(with maximum output of 5 dBm), and AMP
3
(with maximum output of 30 dBm) are arranged in series, while bias circuits
75
and
76
are provided with respect to the AMP
2
and AMP
3
of the later stages, and a connection form is selected by switching switch circuits S
71
. S
72
, S
73
and S
74
, so as to realize an appropriate power amplification.
However, as can be seen from a gain diagram shown in
FIG. 3B
, in the conventional amplifier circuit described above, there are cases for outputting the power that is lower by as much as 25 dB at most with respect to the maximum output power 30 dBm of AMP
3
or the maximum output power 5 dBm of AMP
2
in a range (B in
FIG. 3B
) of the output power between 5 dBm and 30 dBm, so that the degradation of the efficiency will be caused. Similarly, even in a range (D in
FIG. 3B
) of the output power between −20 dBm and 5 dBm, there is an increase of the consumed power due to the degradation of the efficiency although it is not as much as that in the range B described above.
Also, as shown in
FIG. 3A
, the gain of each stage is usually about 25 dB, so that it is difficult to improve the degradation of the efficiency considerably by the method described above. In this regard, it is also possible to consider a method using a greater number of amplification stages, but in such a case, the minimum unit for the amplification stages that is practically feasible is expected to be 10 dB to 15 dB corresponding to the gain per one stage of a transistor.
In this case, there is a need to align the input/output impedance of each stage, and a conversion up to a higher impedance may be required instead of the ordinarily required conjugate matching of adjacent transistors, which can cause an increase of losses or a complication of a circuit configuration.
For this reason, conventionally, a method for optimizing the load line of the amplifier of arbitrary stage according to the output power has been proposed.
FIG. 4A
shows a circuit for realizing this conventional optimization method schematically.
A circuit shown in
FIG. 4A
realizes a method for switching an effective transistor size of the amplifier, where a plurality of amplifiers
14
a
and
14
b
are connected in parallel, while input switches Si
1
and Si
2
and output switches So
1
and So
2
are provided at the input side and the output side of these transistors
14
a
and
14
b
respectively, and input signals entered from a variable matching circuit
13
i
are entered into a transistor with appropriate gate length or emitter area by switching the switches Si
1
, Si
2
, So
1
and So
2
and amplified signals are outputted to a variable matching circuit
130
. At this point, the matching to a matching condition suitable for a respective transistor size is made by the variable matching circuits
13
i
and
13
o.
In such a conventional amplifier circuit, as a result of selectively combining a plurality of transistors
14
a
and
14
b
appropriately, the unnecessary power consumption can be reduced by reducing the number of transistors that are effective at low output power so as to reduce currents and vary the maximum value thereby maximizing the efficiency at the low output.
In the circuit shown in
FIG. 4A
, the maximum output power is reduced to ½ by reducing the transistor size to ½, so that the efficiency can be maximized for the power in a narrow range of about 3 dB. However, in order to control a range as wide as 24 dB as in the case of
FIGS. 3A and 3B
, 24/3=8 so that as many as 2
8
=256 of divided transistor cells would be required.
Also, in the circuit shown in
FIG. 4A
, there is a need to satisfy the matching condition even when the slope of the load line changes from BK1 to BK2, so that there is a need to change the matching circuit simultaneously. Such a variable matching circuit can be realized by any of a circuit shown in
FIG. 5A
in which a variable inductance
11
and a variable capacitor
12
are combined, a circuit shown in
FIG. 5B
in which distributed constant circuits
14
to
16
are connected through switches S
1
and S
2
, and a circuit shown in
FIG. 5C
in which matching circuits
13
a
and
13
b
of different types
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