High frequency ceramic multi-layer substrate

Details High frequency ceramic multi-layer substrate High frequency ceramic multi-layer substrate

1993-04-01

1995-02-07

Pascal, Robert J.

Wave transmission lines and networks

Long line elements and components

Strip type

257664, 257728, H01P 115

Patent

active

053878884

ABSTRACT:
A high frequency ceramic multi-layer substrate includes a stripline embedded between two dielectric layers having ground electrodes at the top surface and at the bottom surface thereof and an electric circuit formed on another dielectric layer applied to one of the ground electrodes. The stripline is connected to the electric circuit through via holes provided through the dielectric layers. The equivalent length from the stripline to the electric circuit is a fourth of the wavelength of an input high frequency signal, to result in a high frequency attenuation circuit. Another high frequency ceramic multi-layer substrate further includes another electrode provided via another dielectric layer of larger dielectric constant to form a capacitor with one of the ground electrodes, and another dielectric layer for forming an electric circuit thereon is applied to the electrode. The stripline is connected to the electric circuit through via holes provided through dielectric layers. The electric circuit may be an impedance matching circuit of the stripline or a direct current bias circuit. This multi-layer structure makes the high frequency substrate compact and improves high frequency characteristics.

REFERENCES:
patent: 4476446 (1984-10-01), Blight
patent: 4875087 (1989-10-01), Miyauchi et al.
patent: 5072142 (1991-12-01), Tanino
patent: 5087896 (1992-02-01), Wen et al.
patent: 5136271 (1992-08-01), Nishioka
"RF Front End Circuit Components Miniaturized Using Dielectric Resonators for Cellular Portable Telephones", Nishikawa, IEICE Transactions, vol. E 74, No. 6, Jun., 1991, pp. 1556-1562.
Microelectronics Journal vol. 16, Mar. 1985, Luton GB pp. 30-37, Gheewala "Packages for ultra-high speed GaAs ICs", *p. 31, paragraph 3.1; figue 1A*.

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