High frequency BiMOS linear V-I converter, voltage multiplier, m

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307495, 307261, 328156, H03B 1900

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active

051516250

ABSTRACT:
A voltage to current converter, voltage multiplier and mixer circuit. At least two differential output, common source, pairs of matched field effect transistors have cross connected drains. Those transistors which do not have their drains connected together have their gates connected together to form a first pair of voltage input nodes. The two cross connections form output nodes providing differential output currents. A pair of impedance transformation, low output impedance, buffer amplifiers have bipolar transistor output stages and a high input field effect transistor input stage. The outputs of the output stages are each respectively connected to a different one of the common sources of the differential connected pairs. The input nodes of the input stages form a second pair of voltage input nodes. A low impedance, bipolar transistor, constant dc current, biasing circuit is connected to the common sources for biasing the field effect transistors of the differential pairs in their saturation region and for biasing the bipolar transistors in their active region.

REFERENCES:
patent: 4458210 (1984-07-01), Horl
patent: 4912520 (1990-03-01), Yamamoto et al.
patent: 4937516 (1990-06-01), Sempel
Khachab et al., "MOS Multiplier/Divider Cell for Analogue VLSI", Electronic Letters, Nov. 9, 1989, vol. 25, pp. 1550-1551.

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