High energy event protection for semiconductor devices

Details High energy event protection for semiconductor devices High energy event protection for semiconductor devices

1988-01-11

1990-11-20

Wojciechowicz, Edward J.

357 13, 357 15, 357 48, 357 86, H01L 2972

Patent

active

049722476

ABSTRACT:
A circuit configuration which provides protection against damage to semiconductor devices, such as integrated circuits or discrete components caused by high energy events. An additional base region is formed in the epitaxial layer collector of a bipolar transistor. The added base region overlaps an isolation region having an opposite conductivity to the epitaxial layer. During a high energy event, the reverse breakdown of the junction formed between the added base region and the epitaxial layer is in parallel with the reverse breakdown of the junction formed between the epitaxial layer and the substrate. The breakdown voltage of the junction formed at the added base region is less than that of the epitaxial layer/substrate breakdown so that less power is dissipated as heat in the silicon. As a result, the likelihood of thermal damage to PN/junctions near silicon-aluminum contacts is reduced.

REFERENCES:
patent: 4400711 (1983-08-01), Avery
patent: 4564855 (1986-01-01), Van Zanten
patent: 4692991 (1987-09-01), Flowers

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