Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2005-07-05
2005-07-05
Sterrett, Jeffrey (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C327S536000
Reexamination Certificate
active
06914791
ABSTRACT:
An improved charge pump circuit is provided using a triple-well structure where the charge pump circuit has a plurality of stages containing N-channel MOSFET devices in which each stage is contained in a P-well within a Deep N-well residing on a P-substrate. Each pump stage is formed in its own P-well and the pumping stages are serially connected from power supply source to the output terminal. Each pumping stage includes a charge transfer device, a first auxiliary device to precharge the gate of the charge transfer device with a voltage from the previous stage, and a second auxiliary device to switch coupling between the charge transfer device and its substrate region to reduce the body effect and increases the capacitive boosting effect. The multiple stages of circuitry are clocked from either a four-phase clock or a two-phase clock.
REFERENCES:
patent: 5610550 (1997-03-01), Furutani
patent: 5815026 (1998-09-01), Santin et al.
patent: 5925905 (1999-07-01), Hanneberg et al.
patent: 5978283 (1999-11-01), Hsu et al.
patent: 5986947 (1999-11-01), Choi et al.
patent: 6046625 (2000-04-01), Menichelli
patent: 6100557 (2000-08-01), Hung et al.
patent: 6130572 (2000-10-01), Ghilardelli et al.
patent: 6130574 (2000-10-01), Bloch et al.
patent: 6212107 (2001-04-01), Tsukada
patent: 6418040 (2002-07-01), Meng
patent: 6496055 (2002-12-01), Li
patent: 6677805 (2004-01-01), Shor et al.
patent: 6677806 (2004-01-01), Bloch
patent: 6812774 (2004-11-01), Kim
patent: 6819162 (2004-11-01), Pelliconi
“A 3.3 V-Only 16 Mb DINOR Flash Memory,” IEEE International Solid State Circuits Conference, Digest of Technical Papers, 1995, pp. 122-123.
“A 5-V-Only 0.6μm Flash EEPROM with Row Decoder Scheme in Triple-Well Structure”, IEEE Journal of Solid State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1540-1545.
On-Chip High-Voltage Generation in MNOS Integrated Circuits Using Improved Voltage Multiplier Technique, IEEE Journal of Solid-State Circuits, vol. 11, No. 3, Jun. 1976, pp. 374-378.
Koji Shimeno
Ogura Tomoko
Park Ki-Tae
Ackerman Stephen B.
Halo LSI, Inc.
Saile George O.
Sterrett Jeffrey
LandOfFree
High efficiency triple well charge pump circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High efficiency triple well charge pump circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High efficiency triple well charge pump circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3389896