High efficiency, small geometry semiconductor devices

Details High efficiency, small geometry semiconductor devices High efficiency, small geometry semiconductor devices

1988-03-03

1990-01-16

LaRoche, Eugene R.

357 59, 357 65, H01L 2972, H01L 2904, H01L 2940, H01L 2348

Patent

active

048947024

ABSTRACT:
A semiconductor device comprising a first region, which is laterally bounded by a second region comprising a countersunk oxide layer and a highly doped polycrystalline silicon layer, which is disposed thereon and is covered by an oxide layer partly countersunk into it. The side edge of the polysilicon layer adjoins a contact zone, which is obtained by diffusion therefrom and is connected via a current path to a zone of a semiconductor circuit element. The upper side of the polysilicon layer is located at a higher level than that of the first region and the contact zone is connected to the said zone of the semiconductor circuit element via an intermediate region located in the first region below the second oxide layer and having a lower doping than the contact zone.

REFERENCES:
patent: 4338138 (1982-07-01), Cavaliere et al.
patent: 4495010 (1985-01-01), Kronzer
patent: 4792837 (1988-12-01), Zazzu

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