Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-06-03
2003-08-12
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06605985
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power charge pump for low supply voltage applications, which is able to supply high DC output currents.
2. Description of the Related Art
Pumps of the above type find a typical application in nonvolatile memories, such as EPROM and flash memories, wherein parallel writing of the cells is envisaged, parallel writing requiring output currents of the order of tenths of mA to meet the ever more demanding speed requirements.
In particular, for this type of memories, it is often required to supply internally the writing voltage of 4.5 V, to be applied to the drain terminals of the cells, without having to supply it from outside. A further requirement is to avoid the use of large capacitive structures outside the auxiliary chip or chips, such as a DC/DC converter.
The basic diagram of a generic known charge pump is shown in
FIG. 1
, wherein a charge pump
1
is formed by a first and a second branch
2
s,
2
d,
parallel to one another and including a single stage, and by a phase-generating stage
7
.
The two branches
2
s,
2
d
have the same structure. In addition, the phase-generating stage
7
is formed by two symmetrical parts which supply phase signals &phgr; and &phgr;N for the first and for the second branch
2
s,
2
d.
Consequently, the corresponding components are designated by the same reference numbers and by a letter s or d according to whether they refer to the first branch
2
s
or to the second branch
2
d.
In detail, each branch
2
s,
2
d
comprises a first switch and a second switch which are connected at an intermediate node
5
s,
resp.
5
d,
and are implemented by a charging transistor
3
s,
resp.
3
d,
and a charge-transfer transistor of NMOS type
4
s,
resp.
4
d.
In particular, the drain terminals of the charging transistors
3
s,
3
d
are connected to a supply line
10
feeding a supply voltage V
DD
. The source terminal of the charging transistor
3
s,
resp.
3
d,
is connected to the intermediate node
5
s,
resp.
5
d,
and the gate terminal of the charging transistor
3
s,
resp.
3
d,
receives a respective control signal V
1
s,
V
1
d.
In addition, the drain terminal of the charge-transfer transistor
4
s,
resp.
4
d,
is connected to the intermediate node
5
s,
resp.
5
d.
In addition, the drain terminal of the charge-transfer transistor
4
s,
resp.
4
d,
is connected to the intermediate node
5
s,
resp.
5
d.
Both source terminals of the charge-transfer transistors
4
s,
4
d
are connected to an output node
11
, and the gate terminal of the charge-transfer transistor
4
s,
resp.
4
d,
receives a respective control signal V
2
s,
V
2
d.
Each branch
2
s,
2
d
further comprises a boosting capacitor
12
s,
resp.
12
d,
which has a first terminal connected to the intermediate node
5
s,
resp.
5
d,
and a second terminal connected to an output
14
s,
resp.
14
d,
of a first
13
s,
resp. a second inverter
13
d.
The inverters
13
s,
resp.
13
d,
belong to the phase-generating stage
7
and each comprise a PMOS transistor
19
s,
resp.
19
d,
and an NMOS transistor
20
s,
resp.
20
d,
connected together in series between the supply line
10
and the ground line
15
. The inverters
13
s,
resp.
13
d,
have a respective input
16
s,
16
d
which receives a respective oscillating signal F, FN, generated by an oscillator
18
. The oscillating signals F, FN are in phase opposition and oscillate between the supply voltage V
DD
and 0 V. Phase signals &phgr; and &phgr;N, in phase opposition to each other, are thus present on the outputs
14
s,
resp.
14
d.
Boosted voltages Vs, resp. Vd are present on the intermediate nodes
5
s,
5
d;
the output node
11
, at an output voltage Vout, supplies a current Iout.
Operation of the charge pump
1
will now be described with reference to the first branch
2
s;
the second branch
2
d
behaves in the same way, but is out of phase by T/2, where T is the period of the oscillator
18
.
When the oscillating signal F coming from the oscillator
18
switches to the high state (V
DD
), the output
14
s
of the first inverter
13
s
is at 0 V, and the boosting capacitor
12
s
charges up to the supply voltage V
DD
through the charging transistor
3
s,
which is on. When the oscillating signal F switches to 0 V, the output
14
s
of the first inverter
13
s
is high (V
DD
), the charging transistor
3
s
is off, and the voltage Vs tends to go to 2V
DD
. In addition, the charge-transfer transistor
4
s
is on and transfers the boosted voltage Vs to the output
11
.
The operation described above is, however, correct only when the charge pump is not required to supply DC current at output. In fact, the maximum output voltage of the charge pump
1
is different according to whether a capacitive load or an ideal DC generator is connected to the output
11
. In fact, in case of a capacitive load, the charge pump
1
must supply current only in the charging transient of the output capacitor, and subsequently must only supply a minimal current in order to compensate any losses. In this case, the current that can be supplied by the charge pump
1
affects only the rapidity of the transient, but does not affect the voltage Vout that may be obtained at output under steady-state conditions. This situation typically occurs when the charge pump
1
is used for driving in parallel the gate terminals of memory cells.
If, instead, the load requires DC current, as when the drain terminals of the memory cells are to be biased during writing, it is necessary to consider the voltage drops &Dgr;V
MP
, &Dgr;VC and &Dgr;V
M4
across the PMOS transistors
19
s,
19
d,
the boosting capacitors
12
s,
12
d,
and the charge-transfer transistors
4
s,
4
d,
and are due to passage of current in these components.
The output voltage Vout alternately follows the trend of the boosted voltages Vs, Vd minus the drops across the charge-transfer transistors
4
s,
4
d.
The obtainable overall waveform of the output voltage Vout, considering the voltage drops mentioned, is illustrated in
FIG. 2
, which shows both the reduction in the maximum value due to the voltage drops &Dgr;V
MP
and &Dgr;V
M4
and the ripple that is due to the boosting capacitors
12
s,
12
d,
the value of which depends upon the sizing of the boosting capacitors
12
s,
12
d.
In particular, hereinafter the impact of the circuit parameters and characteristics of the charge pump
1
on the voltage drops &Dgr;V
MP
, &Dgr;VC and &Dgr;V
M4
is evaluated. Also in this case, reference will be made to the PMOS transistor
19
s,
the charge-transfer transistor
4
s
and the boosting capacitor
12
s
of the first branch, and the ensuing description also applies to the second branch
2
d.
Calculation of &Dgr;V
MP
When the oscillating signal F is low (0 V), the PMOS transistor
19
s
is on. On the assumption that across the PMOS transistor
19
s
there is a voltage drop &Dgr;V
MP
having a low value, the PMOS transistor
19
s
works in the ohmic region. Consequently, the current Iout that flows in the PMOS transistor
19
s,
and then in the boosting capacitor
12
s,
in the charge-transfer transistor
4
s
and then to the output
11
can be expressed, to a first approximation, as
I
o
u
t
=
μ
P
W
P
L
P
C
o
x
(
V
D
D
-
|
V
t
h
P
|
)
Δ
V
M
P
where &mgr;
P
is the electronic mobility, C
ox
is the capacitance of the gate oxide, W
P
/L
P
is the aspect ratio, and V
thP
is the threshold voltage of the PMOS transistor
19
s.
We thus obtain
Δ
V
M
P
=
I
o
u
t
μ
P
W
P
L
P
C
o
x
(
V
D
D
-
|
V
t
h
P
|
)
The electronic mobility and the capacitance of the oxide are preset process parameters. The designer can therefore act only on the
Fontana Marco
Oddone Giorgio
Pagliato Mauro
Rolandi Paolo
Bennett II Harold H.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Zweizig Jeffrey
LandOfFree
High-efficiency power charge pump supplying high DC output... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-efficiency power charge pump supplying high DC output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-efficiency power charge pump supplying high DC output... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073481