High-efficiency multiplier and multiplying method

Details High-efficiency multiplier and multiplying method High-efficiency multiplier and multiplying method

1998-09-18

2001-09-04

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06286024

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multiplier used as an arithmetic circuit such as a data processor, a microprocessor, etc. and a multiplying method which is executed in the multiplier.
2. Description of the Prior Art
In recent years, in the multimedia processing intended for audio data, image data, etc., it has been requested to execute plural sets of multiplication processes by using a bit width (e.g., 16 bit) which is smaller than a data bit width (e.g., 32 bit) of a processor. But a high-speed multiplication has its limits. Therefore, in order to execute the plural sets of multiplication, the multiplication is carried out in parallel plural times by utilizing such smaller bit width (e.g., four parallel multiplication). It is a matter of course that the multiplication in a normal bit width (e.g., 32 bit) must be also handled.
FIG.1
is a view showing an example of a conventional circuit which has a 32 bit×32 bit multiplication function and four sets of 16 bit×16 bit parallel multiplication function together. A 32 bit×32 bit multiplier
51
is operated to execute the 32 bit×32 bit multiplication, whereas four 16 bit×16 bit multipliers
52
a,
52
b,
52
c,
52
d
are operated simultaneously to execute the four sets of 16 bit×16 bit parallel multiplication.
However, in case an occupied area of a multiplier circuit becomes an issue, all the multiplier circuits
51
,
52
a,
52
b,
52
c,
52
d
cannot be incorporated like the above. For this reason, the multiplication must be handled only by the 32 bit×32 bit multiplier
51
.
FIG.2
is a view showing an example of a conventional circuit which executes the 16 bit×16 bit multiplication and the 32 bit×32 bit multiplication by using the 32 bit×32 bit multiplier only. In order to execute the 16 bit×16 bit multiplication, the 32 bit×32 bit multiplier is separated into four multiplication blocks
61
a,
61
b,
61
c,
61
d
and then the multiplication is executed by using twice the multiplication block
61
a
and the multiplication block
61
d
in which data propagation is not overlapped. Also, in order to execute the 32 bit×32 bit multiplication, the multiplier can be used as the normal 32 bit×32 bit multiplier. In both cases of the 32 bit×32 bit multiplication and the 16 bit×16 bit multiplication, outputs of the multiplication block
61
c
and the multiplication block
61
d
are outputs of the multiplication result. In this case, if the 16 bit×16 bit multiplication is to be executed, a function for cutting off carry propagation is needed between the multiplication block
61
a
and the multiplication block
61
d
not to cause interference of data.
In the following explanation, assuming that a(multiplicand)×b(multiplicator) is expressed as <(m−1):0> in m-bit data, where 0 is a least significant bit and (m−1) is a most significant bit. Assuming that, in the 32 bit×32 bit multiplication, the multiplicand of input data being represented by two's complement is expressed as x<
31
:
0
> and the multiplicator thereof is expressed y<
31
:
0
>. Also, assuming that, in four sets of the 16 bit×16 bit multiplication, the multiplicands of input data being represented by two's complement are expressed as a
1
<
15
:
0
>, a
2
<
15
:
0
>, a
3
<
15
:
0
>, and a
4
<
15
:
0
> respectively, and also the corresponding multiplicators thereof are expressed b
1
<
15
:
0
>, b
2
<
15
:
0
>, b
3
<
15
:
0
>, and b
4
<
15
:
0
> respectively.
In order to respond to four sets of the 16 bit×16 bit parallel multiplication, selectors Sel
1
, Sel
3
, Sel
5
, Sel
7
for selecting multiplicand data and also selectors Sel
2
, Sel
4
, Sel
6
, Sel
8
for selecting multiplicator data are attached to preceding stages of data input ports of the multiplication blocks
61
a,
61
b,
61
c,
61
d
respectively.
The lower 16-bit multiplicand data x<
15
:
0
> in the 32 bit×32 bit multiplication and also the multiplicand data a
1
<
15
:
0
>, a
3
<
15
:
0
> in four sets of the 16 bit×16 bit parallel multiplication are input into the selector Sell. The lower 16-bit multiplicator data y<
15
:
0
> in the 32 bit×32 bit multiplication and also the multiplicator data b
1
<
15
:
0
>, b
3
<
15
:
0
> in four sets of the 16 bit×16 bit parallel multiplication are input into the selector Sel
2
. Similarly, the upper 16-bit multiplicand data x<
31
:
16
> in the 32 bit×32 bit multiplication and 0 are input into the selector Sel
3
. The lower 16-bit multiplicator data y<
15
:
0
> in the 32 bit ×32 bit multiplication and 0 are input into the selector Sel
4
. Then, the lower 16-bit multiplicand data x<
15
:
0
> in the 32 bit×32 bit multiplication and 0 are input into the selector Sel
5
. The upper 16-bit multiplicator data y<
31
:
16
> in the 32 bit×32 bit multiplication and 0 are input into the selector Sel
6
. Similarly, the upper 16-bit multiplicand data x<
31
:
16
>in the 32 bit×32 bit multiplication and also the multiplicand data a
2
<
15
:
0
>, a
4
<
15
:
0
> in four sets of the 16 bit×16 bit parallel multiplication are input into the selector Sel
7
. The upper 16-bit multiplicator data y<
31
:
16
>in the 32 bit×32 bit multiplication and also the multiplicator data b
2
<
15
:
0
>, b
4
<
15
:
0
> in four sets of the 16 bit×16 bit parallel multiplication are input into the selector Sel
8
.
Next, an operation of the multiplier constructed as above will be explained. First, in the case of 32 bit×32 bit multiplication, in the multiplication block
61
a,
the multiplicand data x<
15
:
0
> is selected by the selector Sel
1
and also the multiplicator data y<
15
:
0
> is selected by the selector Sel
2
. Similarly, in the multiplication block
61
b,
the multiplicand data x<
31
:
16
> is selected by the selector Sel
3
and also the multiplicator data y<
15
:
0
> is selected by the selector Sel
4
. In the multiplication block
61
c,
the multiplicand data x<
15
:
0
> is selected by the selector Sel
5
and also the multiplicator data y<
31
:
16
> is selected by the selector Sel
6
. Similarly, in the multiplication block
61
d,
the multiplicand data x<
31
:
16
> is selected by the selector Sel
7
and also the multiplicator data y<
31
:
16
> is selected by the selector Sel
8
. In the same manner as in the usual case, if partial products are generated from input data and then cumulative addition of the partial products is executed, the result of 32 bit×32 bit multiplication can be derived.
Then, in the case of 16 bit×16 bit multiplication, arithmetic operation will be executed in the following order. Four sets of the 16 bit×16 bit parallel multiplication to be calculated are set in the order of multiplicand and multiplicator like a first set: a
1
<
15
,
0
>, b
1
<
15
:
0
>, a second set: a
2
<
15
,
0
>, b
2
<
15
:
0
>, a third set: a
3
<
15
,
0
>, b
3
<
15
:
0
>, and a fourth set: a
4
<
15
,
0
>, b
4
<
15
:
0
>. The first and second sets are executed in the first arithmetic cycle and then the third and fourth sets are executed in the next arithmetic cycle.
To begin with, in the first arithmetic cycle, input data are selected by the selectors Sel
1
, Sel
2
so as to input the multiplicand a
1
<
15
,
0
>, the multiplicator b
1
<
15
:
0
>into the multiplication block
61
a.
Also, input data are selected by the selectors Sel
7
, Sel
8
so as to input the multiplicand a
2
<
15
,
0
>, the multiplicator b
2
<
15
:
0
> into the multiplication block
61
d.
In this case, in order to avoid unnecessary data propagation in the cumulative addition, in the multiplication block
61
b
and the multiplication block
61
c,
input data 0 are selected a

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