Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-02-08
2001-03-06
Kim, Jung Ho (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S390000
Reexamination Certificate
active
06198340
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor integrated circuits and in particular to pump circuits used with semiconductor memory devices.
2. Description of Related Art
Pump circuits have become an important function in semiconductor memories for providing internal voltages higher than the voltage applied to the memory chip. The higher internal voltages created by pump circuits are used with specific functions that cannot be designed to operate at the lower chip voltage. This allows a low voltage to be applied to the chip for the use with most functions to lowers the power dissipation and allow higher levels of integration. One of the more critical applications of a pump circuit is to provide a bias voltage for word line drive circuits. The higher voltage for the wordline drive circuit is necessary to enhance the reading and writing current from the memory cell. The pump circuits generally in use include a booster circuit to produce the higher voltage and some form of a pass gate to connect the charge on capacitors of the booster circuit to an output load including an integrating capacitance to help smooth out the resulting voltage.
In U.S. Pat. No. 5,222,042 (Ichiguchi) a boost circuit for DRAM wordline is shown which boosts the wordline signal and minimizes the effect of capacitor leakage by using two boost circuits. In U.S. Pat. No. 5,134,317 (Otah) a charge pump circuit for a DRAM is disclosed in which the time to charge the boost capacitor is reduced. In U.S. Pat. No. 4,673,829 (Gupta) discloses a charge pump for use in programming a memory array that minimizes leakage current for unselected cells.
In “A High Efficiency CMOS Voltage Doubler” by Pierre Favrat, IEEE Journal of Solid State Circuits, Vol. 33, No. 3, March 1998, a voltage doubler is discussed using a charge pump cell and improved serial switches. An fully integrated charge pump is shown with an efficiency of seventy five percent whereas efficiencies of up to ninety five percent were attained using external capacitors. In “An Experimental 1.5-V 64-Mb DRAM” by Nakagome et al., IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991, low voltage circuit technologies for high density DRAM's is discussed including a wordline driver with charge pump circuit achieving a high boost ratio.
One of the problems with pump circuits is the threshold voltage of the pass gate transistor which reduces the amount of charge that can be transferred to the output of the pump circuit. A pass gate transistor that is not fully turned on has a high threshold voltage. Solving this problem can lead to driving the gate of the pass gate transistor to a high voltage, 3Vcc, and can lead to breakdown problems in the circuitry driving the gate of the pass gate transistor. Other approaches that try to eliminate the high gate voltage have difficulties keeping the pass gate transistors fully turned on and provide a low conductance for transferring charge to the output from a booster circuit. There is also a possibility of latch up because a well bias cannot be maintained to the highest voltage which potentially leads to a circuit latch up.
SUMMARY OF THE INVENTION
In this invention is disclosed an efficient pump circuit in which the maximum voltage is the output voltage plus a threshold voltage of the pass gate transistor. High conductance in the pass gate is provided by pairing an NMOS and a PMOS transistor to be on simultaneously in one half of a clock period and another NMOS and PMOS pair to be on simultaneously in the second half of the clock period. The two pairs of pass gate transistors have a low combined conductance allowing a shorter time period to transfer charge to an output capacitor. This allows the output capacitor voltage to raise more quickly and in turn permits a higher clock frequency as a result of the charging efficiency resulting from the low conductance of the pass gates.
The two pairs of transistors in the two pass gates are driven by two complimentary boosted voltages from a booster circuit that is driven by two complimentary booster signals. Each pass gate connects charge from the booster circuit to the output capacitor and is on during a different portion of the clock period. This configuration provides a very efficient pump circuit. The efficiency of the pump circuit is a measured by the ratio of the output current of the pump circuit compared to the total current required to produce a pump circuit output which includes the booster circuit, the boost voltages, any required external circuitry and any gate control of the pass gates.
The booster circuit comprises two cross coupled circuits each receiving a boost signal through coupling capacitors to produce a boosted signal that is twice the circuit bias Vcc. The two boost signals are clocked to be complimentary to each other and produce two complementary boosted signals. Each boosted signal is connected to the pump circuit output through a pass gate circuit. A first pass gate circuit is driven to be on full during the first half of a clock period and a second pass gate circuit is driven to be on full during the second half of a clock period.
The two pass gate circuits are each comprised of an N-channel and a P-channel transistor pair connected in parallel between the boosted signals and the output of the pump circuit. The gates of the transistor pair are driven separately, but the transistor pairs are driven such that both transistors of a pair are turned on and off together and provide a low conductance when turned on. The transistor pair of the first pass gate circuit is turned on in the first half of a clock period and are turned off in the second half of a clock period. The transistor pair of the second pass gate circuit is turned on in the second half of a clock period and are turned off in the first half of a clock period. The gate voltages connected to the N-channel and P-channel transistor pair in each pass gate circuit are controlled to be either zero volts or a voltage that is equal to the desired output voltage plus the threshold voltage of the N-channel pass gate transistors. Thus the transistors in the pass gate circuits are either off or fully turned on. The P-channel transistors in each pass gate circuit are placed into an N-well that is biased to the highest circuit voltage to prevent circuit latch up.
REFERENCES:
patent: 4673829 (1987-06-01), Gupta
patent: 5134317 (1992-07-01), Ohta
patent: 5222042 (1993-06-01), Ichiguchi
patent: 5600277 (1997-02-01), Koelling
patent: 5748032 (1998-05-01), Baek
patent: 5933047 (1999-08-01), Zhu et al.
Nakagome et al., “An Experimental 1.5-V 64-Mb DRAM,” IEEE vol. 26, No. 4, 1991, pp. 465-471.
Favrat et al., “A High-Efficiency CMOS Voltage Doubler”, IEEE, vol. 33, No. 3, 1998, pp. 410-416.
Ting Tah-Kang Joseph
Wang Gyh-Bin
Wang Ming-Hung
Ackerman Stephen B.
Etron Technology Inc.
Kim Jung Ho
Saile George O.
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