Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2001-02-13
2002-09-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S589000, C363S059000
Reexamination Certificate
active
06448842
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a high-efficient bidirectional voltage boosting device.
BACKGROUND OF THE INVENTION
As is known, inside single-supply non-volatile memories, use is made of both positive and negative voltage boosting devices, such as charge pumps, that generate internally the required voltages to carry out programming, reading, and erasing. The area provided for these charge pumps represents a significant fraction (typically approximately 10%) of the overall surface area of the integrated device. Normally, inside the device, the positive charge pumps are distinct from the negative ones, thus making the bulk problem even more serious.
Both positive and negative charge pump architectures are known, including a certain number of stages, each comprising a (high-value) boosting capacity, and a switch which is closed or opened in counterphase with the adjacent stage. Charge is transferred from one stage to another (towards the output for positive pumps, towards the supply stage for negative pumps), as controlled by complementary phase signals. The switch is formed y diodes (for example MOS transistors, which have gate and drain terminals connected to one another), or by MOS transistors.
The main problem with using diodes is associated with the threshold voltage of the diodes, which involves firstly dissipation, and secondly reduction of the maximum voltage at the output of the charge pump. In general, for a positive charge pump, if N is the number of stages and V
DD
is the supply voltage, the asymptotic value of the output voltage V
OUT
is equal to:
V
OUT
=(
N+
1) (
V
DD
)−
NV
T
,
where V
T
is the threshold voltage of the diodes.
In the case of negative pumps, the asymptotic value of the output is:
V
OUT
=(
N
+1) (i V
DD
−V
T
)
The solution which uses NMOS transistors is intended to solve the above-described problem, and requires the use of four phase signals, i.e., two driving signals for the high capacities, and two driving signals for the switches.
However, this solution also is not free from problems. In fact, MOS transistors also have threshold voltage problems, and in addition the dependence of the threshold voltage on the source-body voltage drop (the so-called body effect) is detrimental in terms of conductivity of the switches, particularly at high voltages, and thus in particular for the stages that are closest to the output.
The problem of the body effect has been solved by isolating the body region of the NMOS transistor through an isolated well (triple-well transistor), and biasing the body well to a voltage set by an appropriate circuit. In the case of NMOS switches, triple-well transistors are typically used.
An embodiment of a positive pump with switches formed by NMOS transistors with four phases and good performance in terms of efficiency, is described in EP-A-0 836 268.
Negative pumps which use the same technique have also been presented (see for example EP-A-0 843 402).
In both cases, the biasing of the wells takes place through a divider, which, in a specific manner to each well, can generate biasing voltages comprised between ground and the output voltage Vour of the charge pump, and can therefore meet the following two requirements:
1. The well of the NMOS transistor that operates as a switch must be biased to a voltage value that is no higher than the minimum potential present at the drain or source terminals, in order to prevent direct biasing of the bulk-source and bulk-drain junctions.
2. The body well of the NMOS transistor that operates as a switch may not be biased to a voltage value that is excessively low, such as to reduce the body effect as far as possible, and therefore maintain adequate conductivity of the NMOS transistor, even at high voltages.
Finally, a two-phase bidirectional charge pump is known, which uses diodes as switches, as described for example in EP-A-0 822 556. In this known bidirectional charge pump, the input stage is provided with a first switch that, when operating as a positive charge pump, connects the input of the pump to the supply line, and otherwise is open; in addition, the output is provided with a second switch, which, when operating as a negative charge pump, connects the output to ground, and otherwise is open.
Since this bidirectional charge pump uses diodes as switches, it is affected by the above-described problems.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a bidirectional voltage boosting device that uses NMOS transistors as switches, such as to obtain the above-described advantages relative to this solution.
According to the present invention, a bidirectional voltage boosting device is provided, the device including a phase generator stage generating phase signals, a charge pump circuit having an input and an output with phase inputs receiving the phase signals, the charge pump circuit having a plurality of voltage boosting stages cascade connected between the input and the output, each voltage boosted stage defining a first and a second transfer node connected to a respective adjacent voltage boosting stage. Each voltage boosting stage includes a storage capacitor with a first and a second terminal, the first terminal of the storage capacitor receiving a first one of the phase signals, the second terminal of the storage capacitor being connected to the second transfer node; a switch element formed by an NMOS transistor having a first and a second conduction terminal and a control terminal, the first and second conduction terminals connected respectively to the first transfer node and to the second transfer node; a voltage boosting capacitor having a first terminal receiving a second one of the phase signals, and a second terminal connected to the control terminal of the switch element; a first precharge circuit connected between the first transfer node and the control terminal of the switch element to control charge transfer from the first node to the second node, the first precharge circuit having an activation terminal receiving a first activation signal; and a second precharge circuit connected between the second transfer node and the control terminal of the switch element to control charge transfer from the second transfer node to the first transfer node, the second precharge circuit having an activation terminal receiving a second activation signal. Ideally, the first and second activation signals are never active simultaneously.
In accordance with another aspect of the invention, a voltage boosting circuit is provided that includes a plurality of voltage boosting stages connected in cascade, each voltage boosting stage connected to adjacent stages by first and second transfer nodes. Each voltage boosting stage includes a switch element with a first terminal coupled to the first transfer node, a second terminal coupled to the second transfer node, and a control terminal; a first precharge circuit having a first terminal coupled to a first transfer node, a second terminal coupled to a control terminal of the switch element, and a control terminal coupled to a first activation signal source, the first precharge circuit configured to control charge transfer from the first transfer node to the second transfer node; and a second precharge circuit comprising a first terminal coupled to the second transfer node, a second terminal coupled to the control terminal of the switch element, and a control terminal coupled to a second activation signal source, the second precharge circuit configured to control charge transfer from the second transfer node to the first transfer node.
REFERENCES:
patent: 5335200 (1994-08-01), Coffman et al.
patent: 5754476 (1998-05-01), Caser et al.
patent: 5912560 (1999-06-01), Pasternak
patent: 6075402 (2000-06-01), Ghilardelli et al.
patent: 6292048 (2001-09-01), Li
patent: 0 822 556 (1998-02-01), None
patent: 0 836 268 (1998-04-01), None
patent: 0 843 402 (1998-05-01), None
Canegallo Roberto
Dozza Davide
Zanuccoli Mauro
Callahan Timothy P.
Jorgenson Lisa K.
Luu An T.
SEED IP Law Group PLLC
STMicroelectronics S.r.l.
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