High efficiency amplifier with reduced parasitic capacitance

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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C257S517000, C257SE29187, C257SE27074

Reexamination Certificate

active

07982282

ABSTRACT:
A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

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Van Rijs, F., et al., Record power added efficiency of bipolar power transistors for low voltage wireless applications, 0-7803-4774-9/98, 1998 IEEE, pp. 957-960.
Washio, K., et al., A .02 um Self-Aligned SiGe HBT Featuring 107-GHz f max and 6.7-ps ECL, 0-7803-5410-9/99, 1999 IEEE, pp. 557-560.
Van Rijs, F., et al., Influence of output impedance on power added efficiency of si-bipolar power transistors, 0-7803-5687 2000 IEEE, pp. 1945-1948.
Hartskeer, D., et al., High Performance SiGeC HBT integrated into a 0.25um BiCMOS technology featuring record 88% power-added efficiency, 0-7803-8331-//04, 2004 IEEE.

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