High drive CMOS output buffer with fast and slow speed controls

Details High drive CMOS output buffer with fast and slow speed controls High drive CMOS output buffer with fast and slow speed controls

1997-05-12

2000-07-25

Kim, Jung Ho

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Delay controlled switch

327393, 327108, 327404, 326 27, 326 87, H03K 17296

Patent

active

060940867

ABSTRACT:
An output buffer is provided which receives an input signal and drives an output terminal. The output buffer has a first driver and a second driver for driving the output terminal to a voltage level corresponding to a logic value of the input signal. The second driver has a greater (current) driving capacity than the first driver. The output buffer also has control circuitry which detects a transition in the logic value of the input signal. In response, the control circuitry generates a particular pulse aligned with the input signal logic value transition having a particular constant voltage level for a predetermined time period. Furthermore, the control circuitry delays the second circuit from driving the output terminal to a complementary voltage level corresponding to the logic value to which the input signal transitions during the predetermined time period.

REFERENCES:
patent: 4421994 (1983-12-01), Puri et al.
patent: 5391939 (1995-02-01), Nonaka
patent: 5708386 (1998-01-01), Chow
patent: 5717343 (1998-02-01), Kwong

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