High-density wirebond chip interconnect for multi-chip modules

Details High-density wirebond chip interconnect for multi-chip modules High-density wirebond chip interconnect for multi-chip modules

1996-06-07

1998-03-03

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

257776, 257784, 257692, 257725, 257208, 257203, 257698, H01L 2316, H01L 2710, H01L 2348, H01L 23055

Patent

active

057239061

ABSTRACT:
A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.

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