High density wire bonding pads for semiconductor package

Details High density wire bonding pads for semiconductor package High density wire bonding pads for semiconductor package

2003-01-27

2004-02-17

Nguyen, Vanthu (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S778000, C257S678000, C438S106000

Reexamination Certificate

active

06693359

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a semiconductor package with bonding pads thereon using spaces above a conductor pattern.
2. Description of the Related Art
A conventional semiconductor package
90
, as shown in FIG.
1
and
FIG. 2
, has a substrate
91
, a conductor pattern
92
consisting of a plurality of copper traces
93
in a specific layout on a side or both sides of the substrate
91
and a solder mask
94
on the substrate
91
and sheltering the conductor pattern
92
. The solder mask
94
is removed at specific portions to exposing the predetermined sections of the traces
93
and to plate nickel and gold layers
95
on the exposed surfaces of the traces
93
such that bonding pads
96
are made on the package
90
.
Please refer to
FIG. 2
, the layers
95
will be attached on top surfaces
931
and opposite lateral sides
932
of the exposed traces
93
of the conductor pattern
92
. It is quite different to control the thickness of the layers
95
on the lateral sides of the trace
93
in plating such that the pitch of the pads
96
must be kept in a larger distance to prevent electromagnetic interference under a condition of larger thickness of the layers
95
on the lateral surfaces
932
shortening the interval of two pads
96
and to prevent two pads
96
short because of the layers
95
on the lateral surfaces
932
touching each other. Therefore, there will be fewer pads
96
can be arranged on the packages within a predetermined interval.
FIG.
3
and
FIG. 4
show the package
90
attaches a die
97
thereon and electrically connects the die
97
with the conductor pattern
92
by wire bonding. Bonding wires
98
(usually are gold wires) bond their both ends to the die
97
and the bonding pads
96
of the package
90
.
The pads
96
have to be arranged at a portion far away from the die
97
to get sufficient amounts of the pads
96
for connection therewith. Under such condition, the bonding wires
98
must be longer and the proportion of defective of bonding the wires
98
will be larger. More important, the size of the package
90
is limited to be smaller.
SUMMARY OF THE INVENTION
The primary objective of the present invention is to provide a semiconductor package, which can arrange more pads thereon in a predetermined interval compared with a conventional semiconductor package can.
According to the objective of the present invention, a semiconductor package of the present invention comprises a substrate with a conductor pattern thereon. The conductor pattern has a plurality of conductive traces in a specific layout. The conductor pattern has at least a conducting portion on which is provided with a conductor member. The conductor members locate at positions above the conducting portion of the conductor pattern with a bottom surface thereof electrically connecting a top surface of the conducting portion. A solder mask is provided on the substrate sheltering the conductor pattern but exposing at least a top surface of the conductor member. Whereby, the conductor can electrically connect an electric device, such as a die, via the conductor members.


REFERENCES:
patent: 2002/0084533 (2002-07-01), Pollock et al.
patent: 2003/0066679 (2003-04-01), Castro et al.

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