High density wire bond BGA

Details High density wire bond BGA High density wire bond BGA

1999-06-14

2001-06-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S106000

Reexamination Certificate

active

06242279

ABSTRACT:

This application is related to application Ser. No. 09/332,427, filed on Jun. 14, 1999, assigned to a common assignee.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices and more particularly, to a method and structure for making high density packaging substrates for wire bonded chips.
(2) Description of the Prior Art
In the field of high density interconnect technology, it is necessary to fabricate a multilayer structure on the substrate to connect integrated circuits to one another. To achieve a high wiring and packing density, many integrated circuit chips are physically and electrically connected to a single substrate commonly referred to as a multi-chip module (MCM). Typically, layers of a dielectric such as a polyimide separate metal power and ground planes in the substrate. Embedded in other dielectric layers are metal conductor lines with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes. Adjacent layers are ordinarily formed so that the primary signal propagation directions are orthogonal to each other. Since the conductor features are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography, it is important to produce patterned layers that are substantially flat and smooth (i.e., planar) to serve as the base for the next layer.
Surface mounted, high pin count integrated circuit packages have in the past been configured using Quad Flat Packs (QFP's) with various pin configurations. These packages have closely spaced leads for making electrical connections distributed along the four edges of the flat package. These packages have become limited by being confined to the edges of the flat package even though the pin to pin spacing is small. To address this limitation, a new package, a Ball Grid Array (BGA) is not so confined because the electrical contact points are distributed over the entire bottom surface of the package. More contact points can thus be located with greater spacing between the contact points than with the QFP's. These contacts are solder balls that facilitate flow soldering of the package onto a printed circuit board.
A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier. The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mils. spacings in regular and staggered array patterns.
Interconnecting lines and vias are planarized by multiple coatings of a dielectric material such as polyimide which are used to achieve an acceptable degree of planarization. Application of multiple coatings of thick polyimide is time-consuming and creates high stress on the substrate.
In the realm of micron and submicron device features, the conducting interconnections that connect the Integrated Circuit to other circuit or system components become relatively more important and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. Circuit performance parameters such as parasitic capacitance and resistance of the metal interconnections increase, thereby degrading the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines.
Recent developments in the creation of semiconductor integrated devices have seen device features being reduced to the micron and sub-micron range. Continued emphasis on improved device performance requires increased device operating speed, which in turn requires that device dimensions are further reduced. This leads to an approach that is applied to Ultra Large Scale Integration (ULSI) devices where multi-levels of metal interconnects are used to electrically interconnect the discrete semiconductor devices on the semiconductor chips. In more conventional approaches, the different levels of interconnect are separated by layers of insulating materials. The various adjacent levels of metal can be interconnected by creating via openings in the interposing insulating layers. Typically, an insulating layer is silicon dioxide. Increased reduction of device size coupled with increased device density requires further reduction in the spacing between the metal interconnect lines in order to accomplish effective interconnects of the integrated circuits. This however is accompanied with an increase in capacitive coupling between adjacent lines, an increase that has a negative impact on device performance and device operating speed. A method must therefore be found whereby devices can be mounted in very close physical proximity without increasing capacitive coupling while also reducing the RC induced time delay of the circuit. One typical approach is to search for insulating layers that have low dielectric constants, ideally the dielectric constant of a vacuum. Another approach is to use electrical conductors for the interconnect lines that have low electrical resistivity thereby reducing the RC time delay. Another approach is to direct the packaging of semiconductor devices in the direction of wafer-like packages. This approach offers the advantages of being able to use standard semiconductor processing equipment and processes while it can readily be adapted to accommodate die shrinkage and to wafer-level burn-in and testing.
The present invention starts with a metal panel, typically made of copper, and takes advantage of a technology known in the art as the Build Up Multilayer (BUM) in combination with thin film deposition techniques to create a substrate for high density packages.
Other Prior Art applications that use metal substrates to package BGA devices consist of Olin's MBGA (U.S. Pat. No. 5,578,869) and MMS's Metal BGA. The MMS approach starts with a 6″ wafer form factor but neither of these approaches use BUM technology or thin film deposition techniques as applied in the manufacturing of large area flat panel displays. The resulting manufacturing cost incurred using this approach is high.
Another Prior Art approach is the approach used by Substrate Technology Inc. for the Ultra BGA. In this approach, the BGA substrate is made by creating the BUM on a metal substrate for the wiring of the printed circuit board. Thin film deposition techniques are however not used in this approach which results in limited line density of the overall package. Line width achieved by using this approach is about 50 u while the spacing between the lines is about 50 u. Fan out for high-density BGA devices can therefore only be achieved by creating multiple layers of metal, which makes the manufacturing of the BGA substrate expensive.
U.S. Pat. No. 5,578,869 (Hoffman et al.) shows a (1) metal base/panel for a package.
U.S. Pat. No. 5,866,942 (Suzuki et al.) discloses (1) a laminate package using polyimide and copper foil patterns.
U.S. Pat. No. 5,1660,738 (Hunter, Jr. et al.) and U.S. Pat. No. 5,509,553 (Hunter, Jr et al.) show (3) a metal layer process (DEMR) (see
FIG. 5A
) that appears to comprise a) sputter plating base b) plating metal (semi-additive plating), see col. 2.
U.S. Pat. No. 5,660,697 (Kawashima et al.) shows a flat panel process (2) using a sputtered SiN dielectric.
U.S. Pat. No. 5,830,563 (Shimoto et al.) discloses a laminate substrate with thin films deposited thereon.
U.S. Pat. No. 5,837,427 (Hwang et al.) shows a (4) BUM process for a metal base/panel PCB.
U.S. Pat. No. 5,525,834 (Fischer et al.) shows a package having a Cu substrate, thin dielectric layers (1-25 um thick) and thin dielectric layers (12 to 75 um), see col. 7 an

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