High density trench isolation for MOS circuits

Details High density trench isolation for MOS circuits High density trench isolation for MOS circuits

1989-12-22

1993-01-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 34, 437 79, H01L 2176, H01L 21306

Patent

active

051790386

ABSTRACT:
A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.

REFERENCES:
patent: 4196440 (1980-04-01), Anantha et al.
patent: 4369565 (1983-01-01), Muramatsu
patent: 4520552 (1985-06-01), Arnould et al.
"Characterization & Modeling Of The Trench Surface Inversion Problem For The Trench Isolated CMOS Technology"; Cham, Chiang, Wenocur, Rung; IEEE 1983 pp. 23-26.
"Deep Trench Isolation For Bipolar Processes"; Malaviya; IBM Techn. Disc. Bulletin vol. 24 No. 11A Apr. 1982; pp. 5578-5580.
"Submicron MOS VLSI Process Technologies"; Arai; IEEE 1983; pp. 19-22.
"A Submicron CMOS Megabit Level Dynamic RAM Technology Using Doped Face Trench Capacitor Cell"; Minegishi, Nakajima, Miura, Harada & Shibata; IEEE 1983 pp. 319-322.
"Depletion Trench Capacitor Technology For Megabit Level MOS dRAM"; Morie, Minegishi & Nakajima; IEEE 1983; pp. 411-414.
"High Speed Latchup-Free 0.5pm Channel CMOS Using Self-Aligned TiSi2 & Deep-Trench Isolation Technologies"; Yamaguchi, Morimoto, Kawamoto, Par, Eiden; IEEE 1983; pp. 522-525.
"Dielectrically Isolated Transistor Structure With Sidewall Inversion Prevention"; Berger & Thiel; IBM Tech. Discl. Bulletin vol. 21 No. 7 Dec. 1978; pp. 2868-2869.

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