Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1997-10-29
2001-02-27
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000
Reexamination Certificate
active
06194283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to an improved process for filling shallow trench isolation structures to minimize void formation therein.
2. Description of the Relevant Art
The fabrication of an integrated circuit involves placing numerous devices in a single semiconductor substrate. Select devices are thereafter interconnected by a conductor which extends over a dielectric which separates or “isolates” the individual devices. Implementing an electrical path across a monolithic integrated circuit thereby involves selectively connecting isolated devices. When fabricating integrated circuits it must therefore be possible to isolate devices built into the substrate from one another. From this perspective, isolation technology is one of the critical aspects of fabricating a functional integrated circuit.
A popular isolation technology used for an MOS integrated circuit involves the process of locally oxidizing silicon. Local oxidation of silicon, or LOCOS, involves oxidizing field regions between devices. The oxide grown in field regions is termed field oxide, wherein field oxide is grown during the initial stages of integrated circuit fabrication, before source and drain implants are placed in device areas or active areas. By growing a thick field oxide in field regions pre-implanted with a channel-stop dopant, LOCOS processing serves to prevent the establishment of parasitic channels in the field regions.
While LOCOS has remained a popular isolation technology, there are several problems inherent with LOCOS. First, a growing field oxide extends laterally as a bird's-beak structure. In many instances, the bird's-beaks structure can unacceptably encroach into the device active area. Second, the pre-implanted channel-stop dopant often redistributes during the high temperatures associated with field oxide growth. Redistribution of channel-stop dopant primarily effects the active area periphery causing problems known as narrow-width effects. Third, the thickness of field oxide causes large elevational disparities across the semiconductor topography between field and active regions. Topological disparities cause planarity problems which become severe as circuit critical dimensions shrink. Lastly, thermal oxide growth is significantly thinner in small field (i.e., field areas of small lateral dimension) regions relative to large field regions. In small field regions, a phenomenon known as field-oxide-thinning effect therefore occurs. Field-oxide-thinning produces problems with respect to field threshold voltages, interconnect-to-substrate capacitance, and field-edge leakage in small field regions between closely spaced active areas.
Many of the problems associated with LOCOS technology are alleviated by an isolation technique known as the “shallow trench process”. Despite advances made to decrease bird's-beak,channel-stop encroachment and non-planarity, it appears that LOCOS technology is still inadequate for deep sub-micron MOS technologies. The shallow trench process is better suited for isolating densely spaced active devices having field regions less than one micron in lateral dimension.
The trench process involves the steps of etching a silicon substrate surface to a relatively shallow depth, e.g., between 0.05 to 0.5 microns, and then refilling the shallow trench with a deposited dielectric. Some trench processes include an interim step of growing oxide on trench walls prior to the trench being filled with a deposited dielectric. After the trench is filled, it is then planarized to complete the isolation structure.
The trench process eliminates bird's-beak and channel-stop dopant redistribution problems. In addition, the isolation structure is fully recessed, offering at least a potential for a planar surface. Still further, field-oxide thinning in narrow isolation spaces does not occur and the threshold voltage is constant as a function of channel width.
The refilling of the isolation trench with a dielectric tends to be performed by a number of chemical vapor deposition (“CVD”) techniques, including atmospheric CVD, low-pressure CVD, and plasma-enhanced CVD. The deposition of films by these methods generally exhibit good electrical and physical properties, however, silane-based CVD tends to have a number of problems. These problems may include, (i) non-conformal coverage, (ii) reentrant angles at the base of the trench, and (iii) void formation during the process of filling the trench. Void formation may occur in shallow trenches with a lateral distance at or below a 0.6 micrometer feature size. Formation of voids within these trenches tends to cause a number of problems. In particular, such voids may open up during the etchback step and subsequently trap moisture, photoresist, or metal from the next deposition. Additionally, voids tend to cause irregularities on the surface of the substrate. These non-planar regions may cause layers subsequently formed above the void to also be non-planar, leading to step coverage problems as more layers are formed.
The formation of voids may occur when deposition of a dielectric is performed on trenches with relatively high aspect ratios. Aspect ratio is defined as the ratio of depth to width. A trench having an aspect ratio of 0.5 has a depth which is half the width of the trench. Void formation typically occurs in trenches having an aspect ratio of greater than 0.8, i.e., when the trench depth approaches the width (or longer).. As depicted in
FIG. 1A-1C
, filling a high aspect ratio isolation trench under a number of CVD conditions may lead to void formation in the trench. As depicted in
FIG. 1A
, a deposition of a fill dielectric within a trench
120
may lead to unequal film thickness in which the film thickness at the top surface
110
of the substrate
100
and upper corners
112
of the trench exceeds that on the bottom
114
and lower walls
116
of the trench
120
. If the sidewalls of the trench
120
are spaced close to each other, deposition of the dielectric upon the comers
112
may occur such that the corners meet before the trench is completely filled, as depicted in
FIG. 1B
, forming a void
118
within the isolation trench. During a subsequent etchback or polish procedure void
118
may be opened, as depicted in FIG.
1
C.
It is therefore desirable to develop a technique for forming a trench isolation structure of narrow lateral distances in which the isolation structure is substantially free of voids. Such a technique is necessary to allow the formation of narrow isolation structures that are substantially free of voids that may compromise the ability of these structures to isolate the individual devices. In addition, this technique would help avoid step coverage problems in subsequent layers, which may be caused by the presence of voids.
SUMMARY OF THE INVENTION
The problems identified above are in large part addressed by the method hereof for forming isolation structures within a semiconductor substrate. That is, the present invention contemplates the formation of a trench isolation structure by using angled spacers to partially fill the trench. The angled spacers are formed laterally adjacent to the sidewall surfaces of the trench such that their exposed lateral edges are non-vertical. The trench may be subsequently filled with a dielectric such that the trench is substantially free of voids.
According to an embodiment of the present invention, a semiconductor topography is provided in which a masking layer is preferably formed above a semiconductor substrate. The masking layer may include a single layer of oxide. Alternatively the masking layer may include two layers, a pad oxide layer underlying a nitride masking layer. The oxide layer may be formed by chemical vapor deposition or thermal oxidation. An opening is formed vertically through the masking layer, and an isolation trench is then etched to a depth below the upper surface of the substrate between the sidewalls of the opening. The resul
Gardner Mark I.
Paiz Robert
Spikes, Jr. Thomas E.
Advanced Micro Devices , Inc.
Bowers Charles
Brewster William M.
Conley Rose & Tayon
Daffer Kevin L.
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