High density ternary content addressable memory

Details High density ternary content addressable memory High density ternary content addressable memory

2011-01-18

2011-01-18

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Associative memories

Compare/search/match circuit

C365S049100, C365S148000, C365S168000

Reexamination Certificate

active

07872889

ABSTRACT:
A content addressable memory device with a plurality of memory cells storing data words. Each data bit in the data words is set to one of three values of a first binary value, a second binary value, and a don't care value. An aspect of the content addressable memory device is the use of a single memory element and an access device in the memory cells. The memory cells are arranged such that each memory cell is electrically coupled to a single bit line, a single match line, and a single word line. The memory elements in the memory cells store low resistance states if the data bit value is the first binary value, high resistance states if the data bit value is the second binary value, and very high resistance states if the data bit value is the don't care value.

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Kostas Pagiamtzis et al., “Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey” IEEE Journal of Solid-State Circuits, vol. 41, No. 3 (Mar. 2006).

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