High density semiconductor memory having diagonal bit lines and

Details High density semiconductor memory having diagonal bit lines and High density semiconductor memory having diagonal bit lines and

1997-09-29

1999-01-26

Nelms, David

Static information storage and retrieval

Interconnection arrangements

Magnetic

365 63, 365 51, 257773, G11C 508

Patent

active

058644962

ABSTRACT:
The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.

REFERENCES:
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patent: 5315542 (1994-05-01), Melzner
patent: 5391901 (1995-02-01), Tanabe
patent: 5396451 (1995-03-01), Ema
patent: 5416734 (1995-05-01), Hidaka et al.
patent: 5566104 (1996-10-01), Shinkawata
"FA 14.6: A 1Gb DRAM for File Applications", T. Sugibayashi et al., ISSC95/Session 14.

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