High density semiconductor chip organization

Details High density semiconductor chip organization High density semiconductor chip organization

1975-06-23

1977-02-01

Wojciechowicz, Edward J.

357 55, 357 68, 357 71, H01L 2710, H01L 2906, H01L 2348

Patent

active

040064921

ABSTRACT:
A semiconductor chip layout including a plurality of logic cells arranged in columns. A cell may encompass one of two different magnitudes of area in the chip; and each column contains only cells having the same area. The layout is particularly appropriate for level sensitive logic systems which utilize both combinatorial as well as sequential networks. The combinatorial (combinational) networks are less orderly and require a greater number of selectable input connections, hence more area, than the sequential circuits. The wide and narrow columnar architecture allows a much greater circuit packing density on a chip, resulting in a substantial increase in the number of circuits for a given chip area. Performance is also increased because of the reduced area required by the sequential circuits.

REFERENCES:
patent: 3475621 (1969-10-01), Weinberger
patent: 3771217 (1973-11-01), Hartman

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