High density ROM in a CMOS gate array

Details High density ROM in a CMOS gate array High density ROM in a CMOS gate array

1986-12-11

1990-02-06

Gossage, Glenn A.

Static information storage and retrieval

Read only systems

Semiconductive

365181, 36518909, 36518911, 307469, 34082591, G11C 1140, H03K 19094

Patent

active

048993085

ABSTRACT:
A memory circuit implemented in a CMOS gate array employs both P-channel and N-channel transistors as memory devices. The use of P-channel memory devices is made possible by providing a level-shifting circuit and a voltage reference circuit to compensate for manufacturing process variations and fluctuations in power supply levels. The reference circuit is made up of a series connection of P-channel FETS that are the same as the memory transistors. The reference voltage produced by the reference circuit tracks variations in the power supply and reflects changes in manufacturing processes so that they are compensated in the output of the level shifting circuit. Performance is further enhanced by clocking load FETS that connect the memory transistors to the voltage source, and density is increased by providing two word lines per row of memory transistors.

REFERENCES:
patent: 4093942 (1978-06-01), Suzuki et al.
patent: 4274147 (1981-06-01), Padgett et al.
patent: 4659948 (1987-04-01), Sunter et al.
patent: 4740721 (1988-04-01), Chung et al.
patent: 4771284 (1988-09-01), Masleid et al.
patent: 4779010 (1988-10-01), Moss

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