High density read-only memory

Static information storage and retrieval – Addressing

Patent

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Details

365104, 36523006, G11C 800

Patent

active

049012851

ABSTRACT:
An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

REFERENCES:
patent: 4301518 (1981-11-01), Klaas
patent: 4314362 (1982-02-01), Klass et al.

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