Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-04-08
2001-11-27
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S255000
Reexamination Certificate
active
06323436
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to high density printed wiring boards (PWBs).
In particular, this invention relates to multilayer high density PWBs having plated through holes (PTHs) and/or vias and surface mounted devices (SMDs).
More particularly, the PWBs of the present invention include novel structure and materials yielding marked improvements in electrical and mechanical properties as well as efficiency in use of component surface area. The fabrication process is surprisingly simpler than might be expected of a highly dense PWB structure and involves the use of conventional fabrication techniques and equipment.
2. Background and Art
The integrated circuit and printed circuit board industries are in need of low cost highly reliable interconnect schemes that support the rapidly increasing input/output (I/O) count in ASICs and microprocessors. There is a growing interest in alternatives to the standard ceramic chip carriers with more conventional printed circuit boards for single and multichip carrier applications. However, for solder surface mount applications, the coefficient of thermal expansion (CTE) mismatch between the packaged chips and the PWB substrate poses reliability problems due to the potential of solder joint cracking during thermal cycling. One means of addressing this issue has been the use of an encapsulant, such as an underchip encapsulant, to reinforce the solder connection joints. But unless the encapsulant is reworkable, there is risk of losing the entire assembly if one or more chips are defective. It would therefore be advantageous to have a printed circuit board that has an overall CTE of about 10 ppm/° C., and a lower weight and lower dielectric constant than that of glass reinforced laminates for the purpose of direct chip attach. If the overall CTE were reduced sufficiently, the need for encapsulant would be obviated.
High performance printed circuit boards require high circuit, component, and interconnection density, including either or both solder surface mount components or additional circuitry layers aligned directly atop plated through holes and/or blind vias. The latter case provides additional wiring density since the redistribution layer is not restricted by the through hole pattern in the circuit board. The printed circuit boards of the present invention are especially useful where the density of plated through holes required to service the I/Os of the surface mount devices is such that there would otherwise be insufficient surface area available for placing pads for solder surface mount attachments interstitial to the plated through hole grid. In addition to scarcity of component surface area, soldering SMCs to the surface pads (lands) of unfilled PTHs is difficult because the solder used for assembly tends to wick down into the holes, resulting in low volume, unreliable solder joints.
The drive for increased circuit and component density in PWBs and in assemblies using them makes it highly desirable to be able to solder surface mount components (SMCs) or to place additional circuitry layers directly over the top of PTHs. This is especially the case when the density of the PTHs required to service the I/Os of the SMCs is such that there is no surface area available for attachment pads interstitial to the PTH grid. Such a condition exists with fine pitch Ball Grid Array (BGA) components and Flip Chip Attach (FCA) integrated circuits (IC).
The following references are useful in presenting background information on some approaches to dealing with high density requirements.
On pages 50-54 of the May, 1996 issue of Electronic Packaging and Production, Howard Green and Michael P. Skinner cite the Micromodule Systems (MMS) approach to cost reduction by reducing the number of steps in making a multichip module. The MMS approach involves merging the power plane with the two signal planes and replacing the copper ground plane with an aluminum backplate/heat dissipator.
MMS has not approached the problem which has been addressed by the inventors herein, which is to minimize stresses caused by differences in CTEs within the structure. In fact, the described MMS approach still includes the steps of providing both a gel encapsulant and a cover to defend against the effects of such stresses. MMS's approach is to reduce the dielectric constant by employing a benzocyclobutene (BCB) photosensitive insulator. Because the BCB is not hydrophillic, the moisture removal steps that the use of polyimide required are eliminated. The inventors herein have used a photoactive thin film redistribution layer (TFRL) dielectric, which has a lower dielectric constant and greater moisture resistance than polyimide.
On pages 45-48 of the May, 1996 issue of Electronic Packaging and Production, Brian J. McDermott has contributed “Photodefined Vias Enable High Density Designs”, in which he states that mechanical drilling of vias that are smaller in diameter than 10 mils is cost prohibitive and requires pads which consume too much real estate for high density PWBs. As a solution to that problem, he proposes using an epoxy-based photoimageable dielectric to define the vias, and states that the approach of using photoimageable dielectric wherein blind vias drop directly from pads, as compared to conventional mechanical drilling and sequential lamination, reduces the number of major process steps from 33 to 17 while doubling the wiring density.
The present invention maintains vacuum lamination and drilling of the dielectric but provides pad-in-via and/or pad-in-PTH geography. Conductive vias having high aspect ratio are selectively filled, for example with a metal-filled, partially cured resin material which flows into the holes under laminating conditions. Vacuum lamination serves also to remove any gases that might be present in the vias. The ends of the filled vias, along with the rest of the smoothed panel surface, are then plated and circuitized. Wiring density is further enhanced when an additional layer of vias is created in a thin film redistribution layer (TFRL). A TRFL surface facing away from the filled vias, having been plated and circuitized, is laminated, its unplated surface facing onto the circuitized plane at which the filled vias surface.
On pages 68-76 of the May, 1966 issue of Electronic Packaging and Production, Roland Heitmann has contributed an article titled “The Ultimate Connections: BGA and Flip Chip Attachments”. The article is useful for its overview of various types of electronic packaging schemes either available commercially or in development, the advantages in choosing one over another for a particular device, and the tradeoffs and problems typical of each.
On pages 177-187 of the Proceedings of the 7th International SAMPE Electronics Conference, held Jun. 20-23, 1994, Gregory E. Homan and David J. Powell of DuPont Company contributed “Fabricating PWBs and MCM-Ls with a New Nonwoven Aramid Reinforcement”. The authors describe a nonwoven aramid reinforcement material for PWBs and laminate-based multichip modules (MCM-Ls) that is commercially available under the I.E. DuPont de Nemours registered trademark THERMOUNT. The authors maintain that the nonwoven aramid material is suitable for PWB, MCM-L, direct chip attach (DCA) and fine pitch surface mount (FP-SMT) because of its low in-plane CTE, low Dk, smoothness, dimentional stability, drillability, low cost and conventional processability in conjunction with high Tg epoxy, and that it has other advantages as well. However, cracking of PTH solder interconnects is still identified on p. 9 of the reference as a problem when the aramid material is incorporated into multilayer PWBs, a problem the authors recommend be solved by continuing to introduce high temperature elongation (HTE) class 3 electrodeposited copper foil. In contrast, the inventors of the present invention have solved the problem of interconnect cracking by combining use of the nonwoven aramid material with PTH backfill and proximity positioning of pad and PTH and/or via.
SUMMARY OF THE IN
Hedrick Jeffrey Curtis
Papathomas Kostas
Rai Amarjit Singh
Tisdale Stephen Leo
Viehbeck Alfred
Beck Thomas A.
Gaffin Jeffrey
International Business Machines - Corporation
Morris Daniel
Norris Jeremy
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