Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-10-23
2001-04-10
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C428S209000
Reexamination Certificate
active
06215320
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to multi-layer printed circuit boards for use in semiconductor automatic test equipment and more particularly a high-density multi-level circuit board assembly for efficiently routing a high number of signal paths to a densely packed contact array.
BACKGROUND OF THE INVENTION
In the field of semiconductor automatic test equipment, multi-level printed circuit boards (PCB's) play a critical role in routing numerous signals between fairly large test subsystems, and relatively small devices under test (DUT's). The equipment, often individually referred to as a “tester”, generates and receives test data signals and test control signals to and from one or more DUT's. Depending on whether the tester is of the “prober” type or “package” type, the tests take place at the wafer and packaged-device levels, respectively.
To functionally test devices at the wafer level, the conventional probe type tester generally includes a test controller, such as a computer, that generates waveforms to be applied to one or more of the wafer DUT's. A test head is disposed downstream of the test controller and includes pin electronics for generating test signals in fairly close proximity to the DUT's to minimize time delays and signal attenuation. Data and control signals are routed from the pin electronics through a probecard that physically interfaces with one or more DUT's on the wafer. The signals generated by the test controller are fed to the DUT's that produce responsive output signals. The probecard captures and transmits the DUT outputs back to the test controller for comparison with sets of expected output values.
Key considerations in the selection of automatic test equipment involve the cost per DUT “site”, testing capabilities of the tester, and device interface flexibility. The cost consideration may be further broken down to initial purchase price of the tester, facilities costs, wafer throughput, and yield. Wafer throughput reflects the number of wafers processed per unit time, while the yield refers to the number of acceptable devices that survive test versus the original volume of devices. Consequently, the more DUT's that can be tested in parallel, the higher the throughput. One area open to improvement in this regard is the construction of a probecard that allows simultaneous testing of fairly large arrays of DUT's such as memory devices.
Conventional probe card constructions often employ a multi-level PCB formed with a peripheral annular array of spaced-apart contact pads for engaging corresponding test head contacts or pogos. The center of the board is formed with a relatively small rectangular opening around which is disposed a plurality of contacts corresponding to the spaced-apart peripheral pads. The contacts and pads are coupled electrically through the multiple layers of the card by cylindrical conductive vias. The vias are formed with a predetermined diameter and disposed vertically through one or more layers of the card to serve as inter-layer paths. An array of formed tungsten needles couples to the contacts and projects inwardly and downwardly toward one or more DUT pads as the opening is registered over the DUT. Each needle is about an inch in length.
In operation, the test head of the tester manipulates the probecard needles for registration over a plurality of DUT contacts. The probecard is then positioned to allow the needles to physically engage the DUT contacts on the wafer. Test signals are then generated by the tester pin electronics and applied to the DUTs in parallel. When the array of DUTs finishes test, the probe card is manipulated to engage another array of DUTs. This process repeats a number of times until the wafer is substantially fully probed.
While the foregoing tester construction is beneficial for its intended applications, it suffers from several disadvantages. For example, under circumstances requiring simultaneous testing of fairly large DUT arrays having 32 or more devices, the use of needles becomes cumbersome and somewhat difficult to implement. Moreover, the lengths of the needles often creates a non-50 ohm environment, due to inductive effects, that often limits the testing bandwidth to about 60 MHz or less.
What is needed and heretofore unavailable is a PCB probecard for use in a tester to efficiently rout a large number of high frequency, impedance matched signal paths through the various layers of the probecard to couple relatively spaced-apart contact pads to corresponding contacts disposed in a densely packed prober array. The high density probe card and method of manufacture of the present invention satisfies these needs.
SUMMARY OF THE INVENTION
The high density probecard and method of manufacture of the present invention provides an efficient and cost-effective way of routing high frequency signals between a test head and an array of DUT's. The improved routing enables a substantial increase in the packing density of respective signal paths without requiring additional board layers. This, in turn, provides compatibility with conventional interface hardware.
To realize the foregoing advantages, the invention in one form comprises a multi-level circuit board for efficiently routing electrical signals. The circuit board includes a contact layer comprising a first substrate and formed with a set of contact pads disposed across a relatively large surface area. The contact layer also includes a set of interconnect contacts corresponding to the contact pads and arrayed in a densely packed surface area. A plurality of subsequent layers are disposed in fixed stacked relationship to the contact layer. Each subsequent layer includes a subsequent substrate, and a conductive pattern formed on the subsequent substrate and defining a plurality of signal paths. Conductive vias are coupled to the contact pads and the engagement contacts and are formed through the contact layer and one or more of the plurality of subsequent layers. The vias communicate with the respective signal paths and include selected sets of staggered vias configured to optimize the routing of the signal paths along the respective subsequent layers.
In another form, the invention comprises a probecard for use in an automatic test system to rout signals between a test controller and a parallel array of devices under test. The probecard includes a contact layer comprising a disk-shaped substrate and formed peripherally with an annular array of relatively spaced-apart contact pads. The contact layer includes a centrally disposed rectangular array of relatively densely packed probe contacts. A plurality of signal layers are disposed in fixed stacked relationship to the contact layer. Each signal layer includes a signal substrate, and a conductive pattern formed on the signal substrate and defining a plurality of signal paths. Conductive vias are coupled to the contact pads and the probe contacts and are formed through the contact layer and one or more of the plurality of signal layers. The vias communicate with the respective signal paths and include selected sets of staggered vias configured to optimize the routing of the signal paths along the respective signal layers.
In yet another form, the invention comprises a massively parallel automatic test system for simultaneously testing an array of devices under test on a wafer. The system includes a test controller and a test head disposed downstream of the test controller. A wafer fixture is positioned beneath the test head for mounting a wafer having a plurality of arrays of devices under test. The system further includes a probecard to rout signals between the test controller and the parallel array of devices under test. The probecard includes a contact layer comprising a disk-shaped substrate and formed peripherally with an annular array of relatively spaced-apart contact pads. The contact layer also includes a centrally disposed rectangular array of relatively densely packed probe contacts. A plurality of signal layers are dispose
Kreisman Lance M.
Metjahic Safet
Tang Minh
Teradyne, Inc.
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