High density power device fabrication process using undercut oxi

Details High density power device fabrication process using undercut oxi High density power device fabrication process using undercut oxi

1994-01-31

1997-07-15

Niebling, John

Fishing, trapping, and vermin destroying

437203, 437 31, 437 6, H01L 21265, H01L 4900

Patent

active

056482833

ABSTRACT:
A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444). Trench (80) defines vertically-oriented source and body layers (86, 90) stacked along oxide layer (460) to form vertical channels on opposite sides of trench (80). Layers (86, 90) have a lateral thickness (88) of the undercut sidewalls (444) and rims (447) spacers. Conductor (94) contacts the N-source and P-body layers, and enhanced P+ region in trench (80).

REFERENCES:
patent: 4070690 (1978-01-01), Wickstrom
patent: 4145703 (1979-03-01), Blanchard et al.
patent: 4325073 (1982-04-01), Hughes et al.
patent: 4587712 (1986-05-01), Baliga
patent: 4656076 (1987-04-01), Vetanen et al.
patent: 4713358 (1987-12-01), Bulat et al.
patent: 4967245 (1990-10-01), Cogan et al.
patent: 4994871 (1991-02-01), Chang et al.
patent: 5019522 (1991-05-01), Meyer et al.
patent: 5089434 (1992-02-01), Hollinger
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5177572 (1993-01-01), Markamai
patent: 5260227 (1993-11-01), Farb et al.
patent: 5270257 (1993-12-01), Shin
patent: 5283201 (1994-02-01), Tsang et al.
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5405794 (1995-04-01), Kim
patent: 5430315 (1995-07-01), Rumennik
Baba, Y., et al, "A Study on a High Blocking Voltage UMOS-FET With a Double Gate Structure," Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Institute of Electrical Engineers of Japan and IEEE Electron Devices Society, Tokyo, Japan, pp. 300-302.
D. Ueda, H. Takagi, and G. Kano, "A New Vertical Power MOSFET Structure with Extremely Reduced On-Resistance", IEEE Trans. Electron Dev. ED-32, No. 1, pp. 2-6, Jan. 1985.
D. Ueda, H. Takagi, and G. Kano, "Deep-Trench Power MOSFET with An Ron Area Product of 160 m.OMEGA.-mm.sup.2," IEEE IEDM Tech. Digest, pp. 638-641, 1986.
H.R. Chang, R.D. Black, V.A.K. Temple, W. Tantraporn and B.J. Baliga, "Ultra Low Specific On-Resistance UMOS FET," IEEE IEDM, pp. 642-645, 1986.
D. Ueda, H. Tagaki, and G. Kano, "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process," IEEE Trans. Electron Dev. ED-34, No. 4, pp. 926-930, Apr. 1987.
H. R. Chang, R. D. Black, V. A. K. Temple, W. Tantraporn, and B. J. Baliga, "Self-Aligned UMOSFET's with a Specific On-Resistance of 1 m.OMEGA.-cm.sup.2," IEEE Trans. Electron Dev. ED-34, No. 11, pp. 2329-2334, Nov. 1987.
H. R. Chang, B. J. Baliga, J.W. Kretchmer, and P.A. Piacente, "Insulated Gate Bipolar Transistor (IGBT) with a Trench Gate Structure," IEEE IEDM Tech. Digest, pp. 674-677, 1987.
S. Mukherjee, M. Kim, L. Tsou, and M. Simpson, "TDMOS--An Ultra-Low On-Resistance Power Transistor," IEEE Trans. Electron Dev. ED-35, No. 12, p. 2459, Dec. 1988.
C. Bulucea, M. R. Kump, and K. Amberiadis, "Field Distribution and Avalanche Breakdown of Trench MOS Capacitor Operated in Deep Depletion," IEEE Trans. Electron Dev. ED-36, No. 11, pp. 2521-2529, Nov. 1989.
K. Shenai, "Optimally Scaled Low-Voltage Vertical Power MOSFET's for High-Frequency Power Conversation," IEEE Trans. Electron Dev. vol. 37, No. 4, Apr. 1990.
K. Shenai, W. Hennessy, M. Ghezzo, D. Korman, H. Chang, V. Temple, and M. Adler, "Optimum Low-Voltage Silicon Power Switches Fabricated Using Scaled Trench MOS Technologies," IEEE IEDM Tech. Digest pp. 793-797, 1991.
K. Shenai, "A 55-V, 0.2-m.OMEGA.-cm.sup.2 Vertical Trench Power MOSFET," IEEE Electron Dev. Lett. EDL-12, No. 3, pp. 108-110, Mar. 1991.
S. Matsumoto, T. Ohno, K. Izumi, "Ultralow Specific on Resistance Umosfet with Trench Contacts for Source and Body Regions Realised By Selfaligned Process," Electronics Letters, vol. 27, No. 18, pp. 1640-1641, Aug. 29, 1991.
Chang, Insulated Gate Bipolar Transistor (IGBT) with a Trench Gate Structure, IEDM Tech. Digest, 1987, pp. 674-677.
Shenai, Optimum Low-Voltage Silicon Power Switches Fabricated Using Scaled Trench MOS Technologies, IEDM Tech. Digest, 1991, pp. 793-797.
Shenai, A 55-V, 0.2-m.OMEGA.-cm.sup.2 Vertical Trench Power MOSFET, Electron Dev. Lett., EDL-12, No. 3, Mar. 1991, pp. 108-110.

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