High density power device fabrication process

Details High density power device fabrication process High density power device fabrication process

1992-08-07

1994-02-01

Thomas, Tom

Fishing, trapping, and vermin destroying

437 40, 437 41, 437 50, H01L 2100, H01L 2102, H01L 21265

Patent

active

052832015

ABSTRACT:
A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48). This area is doped to form a source layer (72) atop the body layer (26') and then trenched to form a second trench (80) having sidewalls aligned to the spacer inner surfaces. Second trench (80) defines vertically-oriented source and body layers (86, 90) stacked along gate oxide layer (60) to form vertical channels on opposite sides of second trench (80).

REFERENCES:
patent: 4070690 (1978-01-01), Wickstrom
patent: 4145703 (1979-03-01), Blanchard et al.
patent: 4325073 (1982-04-01), Hughes et al.
patent: 4587712 (1986-05-01), Baliga
patent: 4656076 (1987-04-01), Vetanen et al.
patent: 4713358 (1987-12-01), Bulat et al.
patent: 4994871 (1991-02-01), Chang et al.
patent: 5019522 (1991-05-01), Meyer et al.
patent: 5089434 (1992-02-01), Hollinger
patent: 5108937 (1992-04-01), Tsai et al.
Shenai, Optimum Low-Voltage Silicon Power Switches Fabricated Using Scaled Trench MOS Technologies, IEDM Tech. Digest, 1991, pp. 793-797.
Shenai, A. 55-V, 0.2-m.OMEGA.-cm.sup.2 Vertical Trench Power MOSFET, Electron Dev. Lett., EDL-12, No. 3, Mar. 1991, pp. 108-110.
Baba, Y., et al., "A Study on a High Blocking Voltage UMOS-FET With A Double Gate Structure," Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Institute of Electrical Engineers of Japan and IEEE Electron Devices Society, Tokyo, Japan, pp. 300-302.
D. Ueda, H. Takagi, and G. Kano, "A New Vertical Power MOSFET Structure with Extremely Reduced On-Resistance-Resistance," IEEE Trans. Electron Dev. ED-32, No. 1, pp. 2-6, Jan. 1985.
D. Ueda, H. Takagi, and G. Kano, "Deep-Trench Power MOSFET with An Ron Area Product of 160 m.OMEGA.-mm.sup.2," IEEE IEDM Tech. Digest, pp. 638-641, 1986.
H. R. Chang, R. D. Black, V. A. K. Temple, W. Trantraporn and B. J. Baliga, "Ultra Low Specific On-Resistance UMOS FET," IEEE IEDM, pp. 642-645, 1986.
D. Ueda, H. Tagaki, and G. Kano, "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process," IEEE Trans. Electron Dev. ED-34, No. 4, pp. 926-930, Apr. 1987.
H. R. Chang, R. D. Black, V. A. K. Temple, W. Tantraporn, and B. J. Baliga, "Self-Aligned UMOSFET's with a Specific On-Resistance of 1 m.OMEGA.-cm.sup.2," IEEE Trans. Electron Dev. ED-34, No. 11, pp. 2329-2334, Nov. 1987.
H. R. Chang, B. J. Baliga, J. W. Kretchmer, and P. A. Piacente, "Insulated Gate Bipolar Transistor (IGBT) with a Trench Gate Structure," IEEE IEDM Tech. Digest, pp. 674-677, 1987.
S. Mukherjee, M. Kim, L. Tsou, and M. Simpson, "TDMOS-An Ultra-Low On-Resistance Power Transistor," IEEE Trans. Electron Dev. ED-35, No. 12, p. 2459, Dec. 1988.
C. Bulucea, M. R. Kump, and K. Amberiadis, "Field Distribution and Avalanche Breakdown of Trench MOS Capacitor Operated in Deep Depletion," IEEE Trans. Electron Dev. ED-36, No. 11, pp. 2521-2529, Nov. 1989.
K. Shenai, "Optimally Scaled Low-Voltage Vertical Power MOSFET's for High-Frequency Power Conversation", IEEE Trans. Electron Dev. vol. 37, No. 4, Apr. 1990.
S. Matsumoto, T. Ohno, K. Izumi, "Ultralow Specific on Resistance Umosfet with Trench Contacts for Source and Body Regions Realised By Selfaligned Process," Electronics Letters, vol. 27, No. 18, pp. 1640-1641, Aug. 29, 1991.

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